Test time reduction using parallel RF test techniques. - Rajesh Mittal; Adesh Sontakke; Rubin A. Parekhji (VTS, 2010)

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. - Rajesh Mittal; Lakshmanan Balasubramanian; Adesh Sontakke; Harikrishna Parthasarathy; Prakash Narayanan; Puneet Sabbarwal; Rubin A. Parekhji (ITC, 2011)

Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. - Prakash Narayanan; Rajesh Mittal; Sumanth Poddutur; Vivek Singhal; Puneet Sabbarwal (VTS, 2011)

Towards adaptive test of multi-core RF SoCs. - Rajesh Mittal; Lakshmanan Balasubramanian; Y. B. Chethan Kumar; V. R. Devanathan; Mudasir Kawoosa; Rubin A. Parekhji (DATE, 2013)

Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. - Prabhat Mishra 001; Masahiro Fujita; Virendra Singh; Nagesh Tamarapalli; Sharad Kumar; Rajesh Mittal (VLSI Design, 2013)

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. - Rajesh Mittal; Mudasir Kawoosa; Rubin A. Parekhji (ITC, 2014)

Towards Single Pin Scan for Extremely Low Pin Count Test. - Mudasir S. Kawoosa; Rajesh K. Mittal; Maheedhar Jalasuthram; Rubin A. Parekhji (VLSID, 2018)