Rajesh Pamula
Orcid: 0000-0002-4647-0425Affiliations:
- University of Washington, Department of Electrical and Computer Engineering, Seattle, WA, USA
According to our database1,
Rajesh Pamula
authored at least 17 papers
between 2018 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control.
IEEE J. Solid State Circuits, 2022
2021
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 0.0023 mm<sup>2</sup>/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression.
IEEE Trans. Biomed. Circuits Syst., 2020
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS.
IEEE J. Solid State Circuits, 2020
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
An All-Digital Fused PLL-Buck Architecture for 82% Average V<sub>dd</sub>-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor.
IEEE J. Solid State Circuits, 2019
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains.
IEEE J. Solid State Circuits, 2019
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018