Signature Analysis with Modified Linear Feedback Shift Registers (M-LFSRs). - Rajesh Raina; Peter N. Marinos (FTCS, 1991)

Functional Verification Methodology for the PowerPC 604 Microprocessor. - James Monaco; David Holloway; Rajesh Raina (DAC, 1996)

Efficient Testing of Clock Regenerator Circuits in Scan Designs. - Rajesh Raina; Robert Bailey; Charles Njinda; Robert F. Molyneaux; Charlie Beh (DAC, 1997)

How Seriously Do You Take Your Possible-Detect Faults? - Rajesh Raina; Charles Njinda; Robert F. Molyneaux (ITC, 1997)

T4: Verification. - Rajesh Raina; Jacob A. Abraham; A. K. Pujari (VLSI Design, 1997)

Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. - Rajesh Raina; Robert F. Molyneaux (Great Lakes Symposium on VLSI, 1998)

Design-for-test methodology for Motorola PowerPC microprocessors. - Magdy S. Abadir; Rajesh Raina (ITC, 1999)

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. - Carol Pyron; Mike Alexander; James Golab; George Joos; Bruce Long; Robert F. Molyneaux; Rajesh Raina; Nandu Tendolkar (ITC, 1999)

DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. - Rajesh Raina; Robert Bailey; Dawit Belete; Vikram Khosa; Robert F. Molyneaux; Javier Prado; Ashutosh Razdan (ITC, 2000)

Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; David Halter; Jim Nissen; Rajesh Raina; Masahiro Ishida; Toshifumi Watanabe (ITC, 2000)

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. - Nandu Tendolkar; Robert F. Molyneaux; Carol Pyron; Rajesh Raina (VTS, 2000)

Testing clock distribution circuits using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; Jim Nissen; David Halter; Rajesh Raina; Masahiro Ishida (ITC, 2001)

A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. - Takahiro J. Yamaguchi; Masahiro Ishida; Mani Soma; David Halter; Rajesh Raina; Jim Nissen (VTS, 2001)

Very Low Cost Testers: Opportunities and Challenges. - Jay Bedsole; Rajesh Raina; Al Crouch; Magdy S. Abadir (IEEE Des. Test Comput., 2001)

Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. - Robert Bailey; A. Metayer; B. Svrcek; Nandu Tendolkar; E. Wolf; Eric Fiene; Mike Alexander; Rick Woltenberg; Rajesh Raina (ITC, 2002)

Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . - Dawit Belete; Ashutosh Razdan; William Schwarz; Rajesh Raina; Christopher Hawkins; Jeff Morehead (ITC, 2002)

valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits. - John Gatej; Lee Song; Carol Pyron; Rajesh Raina; Tom Munns (ITC, 2002)

A Wavelet-Based Timing Parameter Extraction Method. - Mani Soma; Welela Haileselassie; Jessica Yan; Rajesh Raina (ITC, 2002)

Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. - Nandu Tendolkar; Rajesh Raina; Rick Woltenberg; Xijiang Lin; Bruce Swanson; Greg Aldrich (VTS, 2002)

Skew measurements in clock distribution circuits using an analytic signal method. - Takahiro J. Yamaguchi; Mani Soma; Jim Nissen; David Halter; Rajesh Raina; Masahiro Ishida (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Is the concern for soft-error overblown? - Rajesh Raina (ITC, 2005)

Have we overcome the challenges associated with SoC and multi-core testing? - Rajesh Raina (ITC, 2005)

What is DFM & DFY and Why Should I Care ? - Rajesh Raina (ITC, 2006)

Achieving Zero-Defects for Automotive Applications. - Rajesh Raina (ITC, 2008)