Retargetable Cache Simulation Using High Level Processor Models. - Rajiv A. Ravindran; Rajat Moona (ACSAC, 2001)

Retargetable Program Profiling Using High Level Processor Models. - Rajiv A. Ravindran; Rajat Moona (HiPC, 2001)

Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. - Scott A. Mahlke; Rajiv A. Ravindran; Michael S. Schlansker; Robert Schreiber; Timothy Sherwood (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Systematic Register Bypass Customization for Application-Specific Processors. - Kevin Fan; Nathan Clark; Michael L. Chu; K. V. Manjunath; Rajiv A. Ravindran; Mikhail Smelyanskiy; Scott A. Mahlke (ASAP, 2003)

Increasing the number of effective registers in a low-power processor using a windowed register file. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (CASES, 2003)

FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths. - Manjunath Kudlur; Kevin Fan; Michael L. Chu; Rajiv A. Ravindran; Nathan Clark; Scott A. Mahlke (CGO, 2004)

Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. - Michael L. Chu; Kevin Fan; Rajiv A. Ravindran; Scott A. Mahlke (IEEE Micro, 2004)

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. - Rajiv A. Ravindran; Pracheeti D. Nagarkar; Ganesh S. Dasika; Eric D. Marsman; Robert M. Senger; Scott A. Mahlke; Richard B. Brown (CGO, 2005)

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (IEEE Trans. Computers, 2005)

Compiler-managed partitioned data caches for low power. - Rajiv A. Ravindran; Michael L. Chu; Scott A. Mahlke (LCTES, 2007)

Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. - Michael L. Chu; Rajiv A. Ravindran; Scott A. Mahlke (MICRO, 2007)

Hardware/software techniques for memory power optimizations in embedded processors. - Rajiv A. Ravindran (2007)