Formal modeling and validation applied to a commercial coherent bus: a case study. - Ganesh Gopalakrishnan; Rajnish Ghughal; Ravi Hosabettu; Abdelillah Mokkedem; Ratan Nalumasu (CHARME, 1997)

The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors. - Ratan Nalumasu; Rajnish Ghughal; Abdelillah Mokkedem; Ganesh Gopalakrishnan (CAV, 1998)

Using "Test Model-Checking" to Verify the Runway-PA8000 Memory Model. - Rajnish Ghughal; Abdelillah Mokkedem; Ratan Nalumasu; Ganesh Gopalakrishnan (SPAA, 1998)

Applications of Hierarchical Verification in Model Checking. - Robert Beers; Rajnish Ghughal; Mark D. Aagaard (FMCAD, 2000)

Verification Methods for Weaker Shared Memory Consistency Models. - Rajnish Ghughal; Ganesh Gopalakrishnan (IPDPS Workshops, 2000)

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. - Roope Kaivola; Rajnish Ghughal; Naren Narasimhan; Amber Telfer; Jesse Whittemore; Sudhindra Pandav; Anna Slobodová; Christopher Taylor; Vladimir A. Frolov; Erik Reeber; Armaghan Naik (CAV, 2009)

Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU. - V. M. Achutha KiranKumar; Aarti Gupta; Rajnish Ghughal (FMCAD, 2012)

Formally Verifying Graphics FPU - An Intel® Experience. - Aarti Gupta; V. M. Achutha KiranKumar; Rajnish Ghughal (FM, 2014)