A single-VDD ultra-low energy sub-threshold FPGA. - Rajsaktish Sankaranarayanan; Matthew R. Guthaus (VLSI-SoC, 2012)

Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. - Rajsaktish Sankaranarayanan; Matthew R. Guthaus (ACM Great Lakes Symposium on VLSI, 2017)

Reducing Variability in Subthreshold Circuits - Rajsaktish Sankaranarayanan (2017)

Chip Package Co-design and Physical Verification for Heterogeneous Integration. - Rajsaktish Sankaranarayanan; Archanna Srinivasan; Arch Zaliznyak; Sreelekha Mittai (ISQED, 2021)