A survey of checker architectures. - Rajshekar Kalayappan; Smruti R. Sarangi (ACM Comput. Surv., 2013)

Surveillance using non-stealthy sensors: A new intruder model. - Amitabha Bagchi; Rajshekar Kalayappan; Surabhi Sankhla (Secur. Commun. Networks, 2014)

SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators. - Rajshekar Kalayappan; Smruti R. Sarangi (ISVLSI, 2015)

Tejas: A java based versatile micro-architectural simulator. - Smruti R. Sarangi; Rajshekar Kalayappan; Prathmesh Kallurkar; Seep Goel; Eldhose Peter (PATMOS, 2015)

Tejas Simulator : Validation against Hardware. - Smruti R. Sarangi; Rajshekar Kalayappan; Prathmesh Kallurkar; Seep Goel (CoRR, 2015)

SecCheck: A Trustworthy System with Untrusted Components. - Rajshekar Kalayappan; Smruti R. Sarangi (ISVLSI, 2016)

FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors. - Rajshekar Kalayappan; Smruti R. Sarangi (ACM Trans. Archit. Code Optim., 2016)

A hardware implementation of the MCAS synchronization primitive. - Srishty Patel; Rajshekar Kalayappan; Ishani Mahajan; Smruti R. Sarangi (DATE, 2017)

ParTejas: A Parallel Simulator for Multicore Processors. - Geetika Malhotra; Rajshekar Kalayappan; Seep Goel; Pooja Aggarwal; Abhishek Sagar; Smruti R. Sarangi (ACM Trans. Model. Comput. Simul., 2017)

Providing Accountability in Heterogeneous Systems-on-Chip. - Rajshekar Kalayappan; Smruti R. Sarangi (ACM Trans. Embed. Comput. Syst., 2018)

ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator. - Rajshekar Kalayappan; Avantika Chhabra; Smruti R. Sarangi (ACM Trans. Model. Comput. Simul., 2020)

A Survey of Cache Simulators. - Hadi Brais; Rajshekar Kalayappan; Preeti Ranjan Panda (ACM Comput. Surv., 2021)

A Formal Approach to Accountability in Heterogeneous Systems-on-Chip. - Rajshekar Kalayappan; Smruti R. Sarangi (IEEE Trans. Dependable Secur. Comput., 2021)

SANNA: Secure Acceleration of Neural Network Applications. - Akash Poptani; Abhishek Mittal; Rishit Saiya; Rajshekar Kalayappan; Sandeep Chandran (VLSID, 2023)

Dynamic Ineffectuality-based Clustered Architectures. - Rajshekar Kalayappan; Sandeep Chandran (CoRR, 2023)

On Decomposing Complex Test Cases for Efficient Post-silicon Validation. - C. Harshitha; Sundarapalli Harikrishna; Peddakotla Rohith; Sandeep Chandran; Rajshekar Kalayappan (ASPDAC, 2024)

CASH: Criticality-Aware Split Hybrid L1 Data Cache. - Shruthi Karunakar; Meenakshi Atkade; Akash Poptani; Rajshekar Kalayappan; Sandeep Chandran (ACM Great Lakes Symposium on VLSI, 2024)

CaH2: Criticality aware Hybrid L2. - Shruthi Karunakar; Rajshekar Kalayappan (HIPCW, 2024)

faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties. - Amrutha Benny; Sandeep Chandran; Rajshekar Kalayappan; Ramchandra Phawade; Piyush P. Kurur (RV, 2024)

Consequence-based Clustered Architecture. - Shruthi Karunakar; Rajshekar Kalayappan; Sandeep Chandran (ACM Trans. Archit. Code Optim., 2025)