Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. - Rakefet Kol; Ran Ginosar; Goel Samuel (ASYNC, 1996)

A Double-Latched Asynchronous Pipeline. - Rakefet Kol; Ran Ginosar (ICCD, 1997)

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. - Wei-Chun Chou; Peter A. Beerel; Ran Ginosar; Rakefet Kol; Chris J. Myers; Shai Rotem; Ken S. Stevens; Kenneth Y. Yun (ASYNC, 1998)

Adaptive synchronization. - Ran Ginosar; Rakefet Kol (ICCD, 1998)

Kin: A High Performance Asynchronous Processor Architecture. - Rakefet Kol; Ran Ginosar (International Conference on Supercomputing, 1998)

RAPPID: An Asynchronous Instruction Length Decoder. - Shai Rotem; Ken S. Stevens; Charles Dike; Marly Roncken; Boris Agapiev; Ran Ginosar; Rakefet Kol; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun (ASYNC, 1999)

An asynchronous instruction length decoder. - Kenneth S. Stevens; Shai Rotem; Ran Ginosar; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun; Rakefet Kol; Charles Dike; Marly Roncken (IEEE J. Solid State Circuits, 2001)

Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. - Alex Branover; Rakefet Kol; Ran Ginosar (DATE, 2004)