WATOPT – An Optimizer for Circuit Applications. - Rakesh Chadha; Kishore Singhal; Jirí Vlach; Ernst Christen; Milan Vlach (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Model Development and Verification for High Level Analog Blocks. - Chandramouli Visweswariah; Rakesh Chadha; Chin-Fu Chen (DAC, 1988)

M3-a multilevel mixed-mode mixed D/A simulator. - Rakesh Chadha; Chin-Fu Chen (ICCAD, 1988)

Extension of a transistor level digital timing simulator to include first order analog behavior. - Rakesh Chadha; Chin-Fu Chen (ICCD, 1988)

M3-a multilevel mixed-mode mixed A/D simulator. - Rakesh Chadha; Chandramouli Visweswariah; Chin-Fu Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Switched-capacitor simulation models for full-chips verification. - Tom Chanak; Rakesh Chadha; Kishore Singhal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (DATE, 1999)