A low power, process invariant keeper for high speed dynamic logic circuits. - Rakesh Gnana David Jeyasingh; Navakanta Bhat (ISCAS, 2008)

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. - Rakesh Gnana David Jeyasingh; Navakanta Bhat; Bharadwaj S. Amrutur (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Phase Change Memory: Scaling and applications. - Rakesh Gnana David Jeyasingh; Jiale Liang; Marissa Caldwell; Duygu Kuzum; H.-S. Philip Wong (CICC, 2012)

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array. - Sukru Burc Eryilmaz; Duygu Kuzum; Rakesh Gnana David Jeyasingh; SangBum Kim; Matthew BrightSky; Chung Lam; H.-S. Philip Wong (CoRR, 2014)

Experimental Demonstration of Array-level Learning with Phase Change Synaptic Devices. - Sukru Burc Eryilmaz; Duygu Kuzum; Rakesh Gnana David Jeyasingh; SangBum Kim; Matthew BrightSky; Chung Lam; H.-S. Philip Wong (CoRR, 2014)