Interconnect enhancements for a high-speed PLD architecture. - Michael D. Hutton; Vinson Chan; Peter Kazarian; Victor Maruri; Tony Ngai; Jim Park; Rakesh H. Patel; Bruce Pedersen; Jay Schleicher; Sergey Y. Shumarayev (FPGA, 2002)

Power estimation and thermal budgeting methodology for FPGAs. - Henry Y. Lui; Chong H. Lee; Rakesh H. Patel (CICC, 2004)

Nanometer design intricacies. - Rakesh H. Patel; Paul Billig (CICC, 2005)

A signal integrity-based link performance simulation platform. - Yuming Tao; William Bereza; Rakesh H. Patel; Sergey Y. Shumarayev; Tad A. Kwasniewski (CICC, 2005)

Multi-protocol embedded PCS IP in a FPGA-SOC. - Ramanand Venkata; Vinson Chan; Binh Ton; Chong Lee; Huy Ngo; Malik Kabani; Tam Nguyen; Arch Zaliznyak; Ning Xue; Steven Shen; Michael Zheng; Michael Lai; et al. (CICC, 2005)

Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. - Shoujun Wang; Haitao Mei 002; Mashkoor Baig; William Bereza; Tadeusz Kwasniewski; Rakesh H. Patel (CICC, 2005)

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. - Rakesh H. Patel; William Bereza (CICC, 2006)

PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. - William Bereza; Yuming Tao; Shoujun Wang; Tad A. Kwasniewski; Rakesh H. Patel (DAC, 2006)

Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. - Walter Fergusson; Rakesh H. Patel; William Bereza (CICC, 2007)

Session 21 - Leveraging the third Dimension. - Rakesh H. Patel; Michael Seningen (CICC, 2008)

Nonlinear behavior study in digital bang-bang PLL. - Albert Vareljian; Mohsen Moussavi; William Bereza; Walter Fergusson; Charles E. Berndt; Rakesh H. Patel (CICC, 2009)