Speculative dynamic vectorization for HW/SW co-designed processors. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (PACT, 2012)

Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (HiPC, 2013)

Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (HPCC/EUC, 2013)

Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (SBAC-PAD, 2013)

Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (ACM Trans. Archit. Code Optim., 2014)

Quantitative characterization of the software layer of a HW/SW co-designed processor. - José Cano 001; Rakesh Kumar 003; Aleksandar Brankovic; Demos Pavlou; Kyriakos Stavrou; Enric Gibert; Alejandro Martínez; Antonio González 001 (IISWC, 2016)

C3D: Mitigating the NUMA bottleneck via coherent DRAM caches. - Cheng-Chieh Huang; Rakesh Kumar 003; Marco Elver; Boris Grot; Vijay Nagarajan (MICRO, 2016)

Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. - Rakesh Kumar 003; Alejandro Martínez; Antonio González 001 (ACM Trans. Comput. Syst., 2016)

Boomerang: A Metadata-Free Architecture for Control Flow Delivery. - Rakesh Kumar 003; Cheng-Chieh Huang; Boris Grot; Vijay Nagarajan (HPCA, 2017)

HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation. - Rakesh Kumar 003; José Cano 001; Aleksandar Brankovic; Demos Pavlou; Kyriakos Stavrou; Enric Gibert; Alejandro Martínez; Antonio Gonzalez (ISPASS, 2017)

Blasting through the Front-End Bottleneck with Shotgun. - Rakesh Kumar 003; Boris Grot; Vijay Nagarajan (ASPLOS, 2018)

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. - Mehdi Alipour; Rakesh Kumar 003; Stefanos Kaxiras; David Black-Schaffer (DATE, 2019)

Freeway: Maximizing MLP for Slice-Out-of-Order Execution. - Rakesh Kumar 003; Mehdi Alipour; David Black-Schaffer (HPCA, 2019)

Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors. - Mehdi Alipour; Stefanos Kaxiras; David Black-Schaffer; Rakesh Kumar 003 (HPCA, 2020)

Uncovering Hidden Instructions in Armv8-A Implementations. - Fredrik Strupe; Rakesh Kumar 003 (HASP@MICRO, 2020)

Fetch-Directed Instruction Prefetching Revisited. - Truls Asheim; Rakesh Kumar 003; Boris Grot (CoRR, 2020)

Shooting Down the Server Front-End Bottleneck. - Rakesh Kumar 003; Boris Grot (ACM Trans. Comput. Syst., 2020)

Twig: Profile-Guided BTB Prefetching for Data Center Applications. - Tanvir Ahmed Khan; Nathan Brown; Akshitha Sriraman; Niranjan K. Soundararajan; Rakesh Kumar 003; Joseph Devietti; Sreenivas Subramoney; Gilles A. Pokam; Heiner Litz; Baris Kasikci (MICRO, 2021)

BTB-X: A Storage-Effective BTB Organization. - Truls Asheim; Boris Grot; Rakesh Kumar 003 (IEEE Comput. Archit. Lett., 2021)

A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors. - Rakesh Kumar 003; Alejandro Martínez; Antonio Gonzalez (CoRR, 2021)

A Specialized BTB Organization for Servers. - Truls Asheim; Boris Grot; Rakesh Kumar 003 (PACT, 2022)

Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control. - Odin Ugedal; Rakesh Kumar 003 (SBAC-PAD, 2022)

Impact of microarchitectural state reuse on serverless functions. - Truls Asheim; Tanvir Ahmed Khan; Baris Kasikci; Rakesh Kumar 003 (WOSC@Middleware, 2022)

Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores. - Rakesh Kumar 003; Mehdi Alipour; David Black-Schaffer (CoRR, 2022)

Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores. - Rakesh Kumar 003; Mehdi Alipour; David Black-Schaffer (ACM Trans. Archit. Code Optim., 2022)

A Storage-Effective BTB Organization for Servers. - Truls Asheim; Boris Grot; Rakesh Kumar 003 (HPCA, 2023)

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings. - Konstantinos Kanellopoulos; Rahul Bera; Kosta Stojiljkovic; F. Nisa Bostanci; Can Firtina; Rachata Ausavarungnirun; Rakesh Kumar 003; Nastaran Hajinazar; Mohammad Sadrosadati; Nandita Vijaykumar; Onur Mutlu (MICRO, 2023)

Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources. - Konstantinos Kanellopoulos; Hong Chul Nam; Nisa Bostanci; Rahul Bera; Mohammad Sadrosadati; Rakesh Kumar 003; Davide Basilio Bartolini; Onur Mutlu (MICRO, 2023)

Weeding out Front-End Stalls with Uneven Block Size Instruction Cache. - Roman Brunner; Rakesh Kumar 003 (MICRO, 2024)

CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions. - Truls Asheim; Magnus Jahre; Rakesh Kumar 003 (SESAME@EuroSys, 2024)

Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology. - Konstantinos Kanellopoulos; Konstantinos Sgouras; F. Nisa Bostanci; Andreas Kosmas Kakolyris; Berkin Kerim Konar; Rahul Bera; Mohammad Sadrosadati; Rakesh Kumar 003; Nandita Vijaykumar; Onur Mutlu (ASPLOS (2), 2025)