20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. - Pratap Narayan Singh; Ashish Kumar 001; Chandrajit Debnath; Rakesh Malik (CICC, 2007)

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. - Pratap Narayan Singh; Ashish Kumar 001; Chandrajit Debnath; Rakesh Malik (CICC, 2008)

Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links. - Raj Kumar Nagpal; Rakesh Malik; Jai Narayan Tripathi (DSD, 2009)

Modelling of Power Distribution Network and Decoupling Network Design for High Speed VLSI Design. - Abhishek Pathak; Sushanta K. Mandal; Raj Kumar Nagpal; Rakesh Malik (DELTA, 2010)

Robust optimization of serial link system for signal integrity and power integrity. - Jai Narayan Tripathi; Raj Kumar Nagpal; Rakesh Malik (NESEA, 2010)

Cost-effective optimization of serial link system for Signal Integrity and Power Integrity. - Raj Kumar Nagpal; Jai Narayan Tripathi; Rakesh Malik (ISQED, 2011)

Damping the cavity-mode anti-resonances' peaks on a power plane by swarm intelligence algorithms. - Jai Narayan Tripathi; Nitin Kumar Chhabra; Raj Kumar Nagpal; Rakesh Malik; Jayanta Mukherjee 001 (ISCAS, 2012)

Maintaining Power Integrity by damping the cavity-mode anti-resonances' peaks on a power plane by Particle Swarm Optimization. - Jai Narayan Tripathi; Raj Kumar Nagpal; Nitin Kumar Chhabra; Rakesh Malik; Jayanta Mukherjee 001 (ISQED, 2012)

Selling to the BRIC: the background to the scholarly publishing market in India. - Rakesh Malik (Learn. Publ., 2012)

Handwritten Musical Document Retrieval Using Music-Score Spotting. - Rakesh Malik; Partha Pratim Roy 001; Umapada Pal 001; Fumitaka Kimura (ICDAR, 2013)

Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization. - Jai Narayan Tripathi; Raj Kumar Nagpal; Nitin Kumar Chhabra; Rakesh Malik; Jayanta Mukherjee 001; Prakash R. Apte (ISQED, 2013)

Decoupling network optimization in high speed systems by mixed-integer programming. - Jai Narayan Tripathi; Ashutosh Mahajan; Jayanta Mukherjee 001; Raj Kumar Nagpal; Rakesh Malik; Nitin Gupta (ISCAS, 2014)

Analysis of a serial link for power supply induced jitter. - Jai Narayan Tripathi; Hiten Advani; Raj Kumar Nagpal; Vijender Kumar Sharma; Rakesh Malik (SoCC, 2015)

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. - Ashish Kumar 001; Chandrajit Debnath; Pratap Narayan Singh; Vivek Bhatia; Shivani Chaudhary; Vigyan Jain; Stéphane Le Tual; Rakesh Malik (ESSCIRC, 2016)

Nonlinear modeling and analysis of buck converter using volterra series. - Hitesh Shrimali; Vijender Kumar Sharma; Jai Narayan Tripathi; Rakesh Malik (ICECS, 2017)

Distortion analysis for a DC-DC buck converter. - Vijender Kumar Sharma; Hitesh Shrimali; Jai Narayan Tripathi; Rakesh Malik (ISOCC, 2017)

A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. - Ashish Kumar 001; Chandrajit Debnath; Pratap Narayan Singh; Vivek Bhatia; Shivani Chaudhary; Vigyan Jain; Stéphane Le Tual; Rakesh Malik (IEEE J. Solid State Circuits, 2017)

Fast Analysis of Time Interval Error in Current-Mode Drivers. - Jai Narayan Tripathi; Ramachandra Achar; Rakesh Malik (IEEE Trans. Very Large Scale Integr. Syst., 2018)