A low-power pipelined MAC architecture using Baugh-Wooley based multiplier. - Rakesh Warrier; Chan Hua Vun; Wei Zhang 012 (GCCE, 2014)

Reconfigurable DSP block design for dynamically reconfigurable architecture. - Rakesh Warrier; Hao Liang 003; Wei Zhang 012 (ISCAS, 2014)

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. - Hao Liang 003; Sharad Sinha; Rakesh Warrier; Wei Zhang 012 (FPL, 2015)

Fracturable DSP Block for Multi-context Reconfigurable Architectures. - Rakesh Warrier; Shanker Shreejith; Wei Zhang 012; Chan Hua Vun; Suhaib A. Fahmy (Circuits Syst. Signal Process., 2017)

Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures. - Rakesh Warrier; Wei Zhang 012; Chan Hua Vun (Circuits Syst. Signal Process., 2017)