Ralf König

Aurang Zaib

Andreas Weichslgartner

ACM Trans. Reconfigurable Technol. Syst., 2013

Providing multiple hard latency and throughput guarantees for packet switching networks on chip.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Hardware Supported Adaptive Data Collection for Networks on Chip.

[BibT_eX]

[DOI]

Andreas Weichslgartner

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012

Grobgranular rekonfigurierbare Mikroarchitekturen zur dynamischen Erzeugung heterogener Prozessorinstanzen in Chip-Multiprozessoren.

[BibT_eX]

[DOI]

PhD thesis, 2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS.

[BibT_eX]

[DOI]

Aurang Zaib

Andreas Weichslgartner

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture.

[BibT_eX]

[DOI]

Timo Stripf

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Hardware prototyping of novel invasive multicore architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors.

[BibT_eX]

[DOI]

Timo Stripf

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Architecture design space exploration of run-time scalable issue-width processors.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010

KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2008

A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.

[BibT_eX]

[DOI]

Timo Stripf

Proceedings of the Design, Automation and Test in Europe, 2008

2004

CARUSO - Project Goals and Principal Approach.

[BibT_eX]

[DOI]

Uwe Brinkschulte

Klaus Dorfmüller-Ulhaas