Implementation of a third-generation 1.1-GHz 64-bit microprocessor. - Georgios K. Konstadinidis; Kevin Normoyle; Samson Wong; Sutikshan Bhutani; Harry Stuimer; Timothy Johnson; Alan P. Smith 002; Daniel Y. Cheung; Fabrizio Romano; Shifeng Yu; Sung-Hun Oh; Victor Melamed; et al. (IEEE J. Solid State Circuits, 2002)

System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume Production. - Wai-Yeung Yip; Scott Best; Wendemagegnehu T. Beyene; Ralf Schmitt (ASP-DAC, 2007)

Simulation and Measurement of On-Chip Supply Noise in Multi-Gigabit I/O Interfaces. - Hai Lan; Ralf Schmitt; Chuck Yuan (ISQED, 2008)

On overcoming the limitations of single-ended signaling for graphics memory interfaces. - Amir Amirkhany; Wendemagegnehu T. Beyene; Chris J. Madden; Aliazam Abbasfar; Dave Secker; Dan Oh; Mohammad Hekmat; Ralf Schmitt; Chuck Yuan (A-SSCC, 2011)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)