Distributed parameter system optimum control design via finite element discretization. - Ralph K. Cavin III; S. C. Tandon (Autom., 1977)

Dynamic Modeling and Control of Digital Communication Networks. - Stephen K. Jones; Ralph K. Cavin III (Computer, 1977)

On the Maximum Average Throughput Rate for a Tandem Node Network. - Stephen K. Jones; Ralph K. Cavin III; J. N. Holyoak (IEEE Trans. Commun., 1977)

An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities. - Stephen K. Jones; Ralph K. Cavin III; Donald A. Johnston (IEEE Trans. Commun., 1980)

Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes. - Stephen K. Jones; Ralph K. Cavin III; William M. Reed (IEEE Trans. Inf. Theory, 1982)

Microelectronic architectures and devices for signal and symbol processing. - Ralph K. Cavin III; Noel R. Strader (Integr., 1983)

Introduction to the SRC design sciences program. - Ralph K. Cavin III (DAC, 1984)

The Impact of ICs on Computer Technology. - Robert M. Burger; Ralph K. Cavin III; William C. Holton; Larry W. Sumney (Computer, 1984)

A perspective on CMOS technology trends. - William C. Holton; Ralph K. Cavin III (Proc. IEEE, 1986)

Bit-level concurrency in real-time geometric feature extractions. - Wentai Liu; Tong-Fei Yeh; William E. Batchelor; Ralph K. Cavin III (CVPR, 1988)

Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. - Wentai Liu; Tong-Fei Yeh; William E. Batchelor; Ralph K. Cavin III (ISCA, 1988)

Rasterization theory, architectures, and implementations for a class of two-dimensional problems. - Wentai Liu; Ralph K. Cavin III (Integr., 1988)

The Semiconductor Research Corporation: Cooperative research. - Ralph K. Cavin III; Larry W. Sumney; Robert M. Burger (Proc. IEEE, 1989)

Hamiltonian Cycles in the Shuffle-Exchange Network. - Wentai Liu; Thomas H. Hildebrandt; Ralph K. Cavin III (IEEE Trans. Computers, 1989)

The design of a high-performance scalable architecture for image processing applications. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III (ASAP, 1990)

P3A: a partitionable parallel/pipeline architecture for real-time image processing. - C. Thomas Gray; Wentai Liu; Thomas A. Hughes; Ralph K. Cavin III; Su-Shing Chen (ICPR (2), 1990)

Design of integrated circuits: directions and challenges. - Ralph K. Cavin III; Jeffrey L. Hilbert (Proc. IEEE, 1990)

Theoretical and Practical Issues in CMOS Wave Pipelining. - C. Thomas Gray; Thomas A. Hughes; Sanjay Arora; Wentai Liu; Ralph K. Cavin III (VLSI, 1991)

A bit-serial VLSI architecture for generating moments in real-time. - Wentai Liu; Su-Shing Chen; Ralph K. Cavin III (IEEE Trans. Syst. Man Cybern., 1993)

Circuit delay calculation considering data dependent delays. - C. Thomas Gray; Wentai Liu; Ralph K. Cavin III; Hong-Yean Hsieh (Integr., 1994)

Timing constraints for wave-pipelined systems. - C. Thomas Gray; Wentai Liu; Ralph K. Cavin III (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. - C. Thomas Gray; Wentai Liu; Wilhelmus A. M. Van Noije; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)

A 250-MHz wave pipelined adder in 2-μm CMOS. - Wentai Liu; C. Thomas Gray; David Fan; William J. Farlow; Thomas A. Hughes; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1994)

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (ARVLSI, 1995)

Concurrent timing optimization of latch-based digital systems. - Hong-Yean Hsieh; Wentai Liu; Ralph K. Cavin III; C. Thomas Gray (ICCD, 1995)

High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (ISCAS, 1995)

A CMOS high-speed data recovery circuit using the matched delay sampling technique. - Jin-Ku Kang; Wentai Liu; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1997)

The delay vernier pattern generation technique. - Gary C. Moyer; Mark Clements; Wentai Liu; Toby Schaffer; Ralph K. Cavin III (IEEE J. Solid State Circuits, 1997)

Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. - Hong-Yean Hsieh; Wentai Liu; Paul D. Franzon; Ralph K. Cavin III (J. VLSI Signal Process., 1997)

Integrated parametric timing optimization of digital systems. - Hong-Yean Hsieh; Wentai Liu; Ralph K. Cavin III (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Delay and power model for current-mode signaling in deep submicron global interconnects. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III (CICC, 2002)

Low-power design methodology for an on-chip bus with adaptive bandwidth capability. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III (DAC, 2003)

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III (ISCAS (5), 2003)

Limits to binary logic switch scaling - a gedanken model. - Victor V. Zhirnov; Ralph K. Cavin III; James A. Hutchby; George Bourianoff (Proc. IEEE, 2003)

A semiconductor industry perspective on future directions in ECE education. - Ralph K. Cavin III; William H. Joyner Jr.; Virginia C. Wiggins (IEEE Trans. Educ., 2003)

Current-mode signaling in deep submicrometer global interconnects. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III; Dale Edwards (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Future devices for information processing. - Ralph K. Cavin III; Victor V. Zhirnov (ESSCIRC, 2005)

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. - Rizwan Bashirullah; Wentai Liu; Ralph K. Cavin III; Dale Edwards (IEEE J. Solid State Circuits, 2006)

The Viability of Cellular Automata Architectures for General Purpose Computing. - Victor V. Zhirnov; Greg Leeming; Kosmas Galatsis; Ralph K. Cavin III (ERSA, 2008)

Boolean Logic and Alternative Information-Processing Devices. - George Bourianoff; Joe E. Brewer; Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov (Computer, 2008)

Emerging Research Architectures. - Ralph K. Cavin III; James A. Hutchby; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. - James A. Hutchby; Ralph K. Cavin III; Victor V. Zhirnov; Joe E. Brewer; George Bourianoff (Computer, 2008)

An Assessment of Integrated Digital Cellular Automata Architectures. - Victor V. Zhirnov; Ralph K. Cavin III; Greg Leeming; Kosmas Galatsis (Computer, 2008)

Scaling beyond CMOS: Turing-Heisenberg Rapproachment. - Victor V. Zhirnov; Ralph K. Cavin III (ESSCIRC, 2009)

Device and Architecture Outlook for Beyond CMOS Switches. - Kerry Bernstein; Ralph K. Cavin III; Wolfgang Porod; Alan C. Seabaugh; Jeff Welser (Proc. IEEE, 2010)

Nanoelectronics Research for Beyond CMOS Information Processing. - George Bourianoff; Michel Brillouët; Ralph K. Cavin III; Toshiro Hiramoto; James A. Hutchby; Adrian M. Ionescu; Ken Uchida (Proc. IEEE, 2010)

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. - Michel Brillouët; George Bourianoff; Ralph K. Cavin III; Toshiro Hiramoto; James A. Hutchby; Adrian M. Ionescu; Ken Uchida (Proc. IEEE, 2010)

Memory Devices: Energy-Space-Time Tradeoffs. - Victor V. Zhirnov; Ralph K. Cavin III; Stephan Menzel; Eike Linn; Sebastian Schmelzer; Dennis Bräuhaus; Christina Schindler; Rainer Waser (Proc. IEEE, 2010)

Prolog to the Section on Science and Engineering Beyond Moore's Law. - Ralph K. Cavin III; Paolo Lugli; Victor V. Zhirnov (Proc. IEEE, 2012)

Science and Engineering Beyond Moore's Law. - Ralph K. Cavin III; Paolo Lugli; Victor V. Zhirnov (Proc. IEEE, 2012)

Nurturing the Growth of a National Infrastructure in Emerging Technologies. - Rafic Z. Makki; Victor V. Zhirnov; Ralph K. Cavin III; Sami Issa; Marco Iansiti (Proc. IEEE, 2018)