An hierarchical VLSI neural network architecture. - Ralph Mason; William Robertson 001; Douglas Pincock (IEEE J. Solid State Circuits, 1992)

Mapping hierarchical neural networks to VLSI hardware. - Ralph D. Mason; William Robertson 001 (Neural Networks, 1995)

Two Improved Algorithms and Hardware Implementations for Key Distribution Using Extended Programmable Cellular Automata. - Chang N. Zhang; Ming Y. Deng; Ralph Mason (ACSAC, 1998)

Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system. - Peter M. Nyasulu; Ralph Mason; W. Martin Snelgrove; Duncan G. Elliott (CICC, 1999)

High speed V.32 trellis encoder/decoder implementation using FPGA. - Anh Dinh; Ralph Mason; Joe Toth (ISCAS (4), 1999)

6.5 mW CMOS low noise amplifier at 1.9 GHz. - Shijun Yang; Ralph Mason; Calvin Plett (ISCAS (2), 1999)

A VLSI Programmable Cellular Automata Array for Multiplication in GF (2n). - Chang N. Zhang; Ming Y. Deng; Ralph Mason (PDPTA, 1999)

A toolset for construction of hybrid intelligent forecasting systems: application for water demand prediction. - Narate Lertpalangsunti; Christine W. Chan; Ralph Mason; Paitoon Tontiwachwuthikul (Artif. Intell. Eng., 1999)

Analog DFT Using an Undersampling Technique. - Ralph Mason; Shing Ma (IEEE Des. Test Comput., 1999)

Mixed Signal DFT at GHz Frequencies. - Ralph Mason; Shing Ma (J. Electron. Test., 1999)

Phase Measurements for Direct Conversion AM Radio Navigation. - Anh Dinh; Ralph Mason; Ron Palmer; Ken Runtz (J. Intell. Transp. Syst., 1999)

A differential bipolar quasi-passive cyclic digital-to-analog converter with 4.416 MSps conversion rate and -77 dB THD. - Mohsen Moussavi; Ralph Mason; Calvin Plett (CICC, 2001)

A 0.18μm CMOS, high Q-enhanced bandpass filter with direct digital tuning. - Chris DeVries; Ralph Mason (CICC, 2002)

A digitally tuned 1.1 GHz subharmonic injection-locked VCO in 0.18μm CMOS. - Hesham Ahmed; Christopher A. DeVries; Ralph Mason (ESSCIRC, 2003)

RF, Q-enhanced bandpass filters in standard 0.18µm CMOS with direct digital tuning. - H. Ahmed; Chris DeVries; Ralph Mason (ISCAS (1), 2003)

A dual edge-triggered phase-frequency detector architecture. - Syed Irfan Ahmed; Ralph D. Mason (ISCAS (1), 2003)

Improving the acquisition time of a PLL-based, integer-N frequency synthesizer. - Syed Irfan Ahmed; Ralph D. Mason (ISCAS (4), 2004)

A 0.18 μm CMOS 900 MHz receiver front-end using RF Q-enhanced filters. - Chris DeVries; Ralph Mason (ISCAS (4), 2004)

An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz. - Ralph Mason; Chris DeVries; Eugene Ivanov (ISCAS (1), 2004)

Bandwidth Expansion in Sigma-Delta PLLs Using Multiphase VCOs. - Igor Miletic; Ralph Mason (CCECE, 2006)

Quantization noise reduction using multiphase PLLs. - Igor Miletic; Ralph Mason (ISCAS, 2006)

A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications. - Reza Yousefi; Ralph Mason (ESSCIRC, 2008)

Subsampling Architecture for Low Power Receivers. - Christopher A. DeVries; Ralph D. Mason (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking. - Ralph Mason; Justin Fortier; Chris DeVries (CICC, 2011)

Phase calibration techniques for injection-locking LO-path based phase-shifting phased-array architectures. - Yasser Soliman; Ralph Mason (RWS, 2012)

Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking. - Ralph D. Mason; Justin Fortier; Christopher A. DeVries (IEEE J. Solid State Circuits, 2012)

A 14b threshold configurable dynamically latched comparator for SAR ADCs. - Tony Forzley; Ralph Mason (SBCCI, 2013)

A novel Injection Locked Rotary Traveling Wave Oscillator. - Zhanjun Bai; Xing Zhou; Ralph Mason (ISCAS, 2014)

Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique. - Zhanjun Bai; Xing Zhou; Ralph D. Mason; Gord Allan (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 65 nm Compact High Performance Fully Synthesizable Clock Multiplier Based on an Injection Locked Ring Oscillator. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (ISCAS, 2018)

A High-Performance Low Complexity All-Digital Fractional Clock Multiplier. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (A-SSCC, 2019)

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. - Dirk Pfaff; Robert Abbott; Xin-Jie Wang; Shahaboddin Moazzeni; Ralph Mason; Raleigh Smith (IEEE J. Solid State Circuits, 2020)

A sub-harmonic injection locking clock multiplier with FLL PVT calibrator. - Nahla T. Abou-El-Kheir; Ralph D. Mason; Mingze Li; Mustapha C. E. Yagoub (Microelectron. J., 2020)

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. - Dirk Pfaff; Muhammad Nummer; Noman Hai; Peter Xia; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; Carson R. Dick; et al. (ISSCC, 2024)

A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited). - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw CH Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (CICC, 2025)

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS. - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw C. H. Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (IEEE J. Solid State Circuits, 2025)