A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither. - Ahmed M. A. Ali; Hüseyin Dinc; Paritosh Bhoraskar; Scott Puckett; Andy Morgan; Ning Zhu; Qicheng Yu; Christopher Dillon; Bryce Gray; Jonathan Lanford; Matthew McShea; Ushma Mehta; et al. (VLSI Circuits, 2016)