Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ∓50 ps jitter. - Ilya I. Novof; John Austin; Ram Kelkar; Don Strayer; Steve Wyatt (IEEE J. Solid State Circuits, 1995)

A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications. - Ram Kelkar; Dave Flye; Anjali Malladi; Joseph Natonio; Chri Scoville; Ken Short; Pradeep Thiagarajan (SoCC, 2005)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)