Logic simulation on vector processors. - Ram Raghavan; John P. Hayes; William R. Martin (ICCAD, 1988)

On randomly interleaved memories. - Ram Raghavan; John P. Hayes (SC, 1990)

Scalar-Vector Memory Interference in Vector Computers. - Ram Raghavan; John P. Hayes (ICPP (1), 1991)

Memory architectures for vector processing. - Ramanathan Raghavan (1991)

Reducing Inerference Among Vector Accesses in Interleaved Memories. - Ram Raghavan; John P. Hayes (IEEE Trans. Computers, 1993)

Cell Broadband Engine Architecture and its first implementation - A performance view. - Thomas Chen; Ram Raghavan; Jason N. Dale; Eiji Iwata (IBM J. Res. Dev., 2007)