SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets. - Sebastian Turullols; Ram Sivaramakrishnan (Hot Chips Symposium, 2012)

The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets. - John R. Feehrer; Sumti Jairath; Paul Loewenstein; Ram Sivaramakrishnan; David Smentek; Sebastian Turullols; Ali Vahidsafa (IEEE Micro, 2013)

Next generation SPARC processor cache hierarchy. - Ram Sivaramakrishnan; Sumti Jairath (Hot Chips Symposium, 2014)

M7: Oracle's Next-Generation Sparc Processor. - Kathirgamar Aingaran; Sumti Jairath; Georgios K. Konstadinidis; Serena Leung; Paul Loewenstein; Curtis McAllister; Stephen Phillips; Zoran Radovic; Ram Sivaramakrishnan; David Smentek; Thomas Wicki (IEEE Micro, 2015)

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts. - Raghu Prabhakar; Ram Sivaramakrishnan; Darshan Gandhi; Yun Du; Mingran Wang; Xiangyu Song; Kejie Zhang; Tianren Gao; Angela Wang; Xiaoyan Li; Yongning Sheng; Joshua Brot; et al. (MICRO, 2024)

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts. - Raghu Prabhakar; Ram Sivaramakrishnan; Darshan Gandhi; Yun Du; Mingran Wang; Xiangyu Song; Kejie Zhang; Tianren Gao; Angela Wang; Karen Li; Yongning Sheng; Joshua Brot; et al. (CoRR, 2024)

Composition of Experts on the SN40L Reconfigurable Dataflow Unit. - Raghu Prabhakar; Ram Sivaramakrishnan; Darshan Gandhi; Yun Du; Mingran Wang; Xiangyu Song; Kejie Zhang; Tianren Gao; Angela Wang; Xiaoyan Li; Joshua Brot; Calvin Leung; et al. (IEEE Micro, 2024)