An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (iSES, 2022)

Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU. - Sujay Kumar Mandal; Muralidhar Pullakandam; Rama Muni Reddy Yanamala (ICCCNT, 2023)

A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (Des. Autom. Embed. Syst., 2023)

Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (Int. J. Circuit Theory Appl., 2024)

High-Speed Power Allocation in NOMA System Using FPGA-Based DNN. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (J. Circuits Syst. Comput., 2024)

A Neural Framework For Handwritten Calendar Parsing and Semantic Content Categorization. - Antoni Gagliard; Rayappa David Amar Raj; Rama Muni Reddy Yanamala (ICYRIME, 2025)

FPGA-Accelerated Sparse Subset Segmentation Using ADMM for High-Resolution Imagery. - Rupali Karthikeyan; Deep Amit Lodaya; Rama Muni Reddy Yanamala; Rayappa David Amar Raj; K. Krishna Prakasha; T. Subeesh; V. Anandkumar; Archana Pallakonda (IEEE Access, 2025)

Smart Grid Intrusion Detection for IEC 60870-5-104 With Feature Optimization, Privacy Protection, and Honeypot-Firewall Integration. - Pedamallu Sai Mrudula; Rayappa David Amar Raj; Archana Pallakonda; Rama Muni Reddy Yanamala; K. Krishna Prakasha; V. Anand Kumar (IEEE Access, 2025)

YOLOv8n-GBE: A Hybrid YOLOv8n Model With Ghost Convolutions and BiFPN-ECA Attention for Solar PV Defect Localization. - Likitha Reddy Yeddula; Archana Pallakonda; Rayappa David Amar Raj; Rama Muni Reddy Yanamala; K. Krishna Prakasha; Mallempati Sunil Kumar (IEEE Access, 2025)

FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition. - Rama Muni Reddy Yanamala; Muralidhar Pullakandam (J. Supercomput., 2025)