Binary decision diagrams for efficient hardware implementation of fast IP routing lookups. - Rama Sangireddy; Arun K. Somani (ICCCN, 2001)

Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. - Rama Sangireddy; Huesung Kim; Arun K. Somani (HiPC, 2002)

Application-Specific Computing with Adaptive Register File Architectures. - Rama Sangireddy; Arun K. Somani (ASAP, 2003)

Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures. - Rama Sangireddy; Huesung Kim; Arun K. Somani (HiPC, 2003)

Scalable, memory efficient, high-speed lookup and update algorithms for IP routing. - Natsuhiko Futamura; Rama Sangireddy; Srinivas Aluru; Arun K. Somani (ICCCN, 2003)

High-speed IP routing with binary decision diagrams based hardware address lookup engine. - Rama Sangireddy; Arun K. Somani (IEEE J. Sel. Areas Commun., 2003)

Register Organization for Enhanced On-Chip Parallelism. - Rama Sangireddy (ASAP, 2004)

Exploiting Quiescent States in Register Lifetime. - Rama Sangireddy; Arun K. Somani (ICCD, 2004)

Low-Power High-Performance Reconfigurable Computing Cache Architectures. - Rama Sangireddy; Huesung Kim; Arun K. Somani (IEEE Trans. Computers, 2004)

Scalable, memory efficient, high-speed IP lookup algorithms. - Rama Sangireddy; Natsuhiko Futamura; Srinivas Aluru; Arun K. Somani (IEEE/ACM Trans. Netw., 2005)

High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. - Prabhu Rajamani; Jatan P. Shah; Vadhiraj Sankaranarayanan; Rama Sangireddy (IPCCC, 2006)

Fast and low-power processor front-end with reduced rename logic circuit complexity. - Rama Sangireddy (ISCAS, 2006)

Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors. - Rama Sangireddy (ITNG, 2006)

Performance Optimization with Scalable Reconfigurable Computing Systems. - Rama Sangireddy; Prabhu Rajamani; Shwetha Gaddam (VLSI Design, 2006)

Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. - Rama Sangireddy (IEEE Trans. Computers, 2006)

On-Chip Adaptive Circuits for Fast Media Processing. - Rama Sangireddy; Arun K. Somani (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. - Jatan P. Shah; Rama Sangireddy (ISCAS, 2007)

Scalable Reconfigurable Architectures for High-Performance Energy-Efficient Multimedia Processing. - Rama Sangireddy; Prabhu Rajamani (Int. J. Comput. Their Appl., 2007)

Register port complexity reduction in wide-issue processors with selective instruction execution. - Rama Sangireddy (Microprocess. Microsystems, 2007)

An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. - Terrell R. Bennett; Rama Sangireddy (VLSI Design, 2008)

Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. - Hui Wang; Sandeep Baldawa; Rama Sangireddy (VLSI Design, 2008)

Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution. - Hui Wang; Rama Sangireddy (Microprocess. Microsystems, 2008)

Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. - Rama Sangireddy; Jatan P. Shah (IEEE Trans. Parallel Distributed Syst., 2008)

Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. - Hui Wang; Rama Sangireddy; Sandeep Baldawa (IEEE Trans. Parallel Distributed Syst., 2009)

Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. - Mangesh K. Kunchamwar; Durga P. Prasad; Pawan Hegde; Poras T. Balsara; Rama Sangireddy (ICPP Workshops, 2010)