A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. - Sanjive Agarwala; Arjun Rajagopal; Anthony M. Hill; Mayur Joshi; Steven Mullinnix; Timothy Anderson; Raguram Damodaran; Lewis Nardini; Paul Wiley; Peter Groves; John Apostol; Michael Gill; et al. (ISSCC, 2007)

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS. - Raguram Damodaran; Timothy Anderson; Sanjive Agarwala; Rama Venkatasubramanian; Michael Gill; Dhileep Gopalakrishnan; Anthony M. Hill; Abhijeet Chachad; Dheera Balasubramanian; Naveen Bhoria; Jonathan Tran; Duc Bui; et al. (VLSI Design, 2012)

Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip. - David Brier; Rama Venkatasubramanian; Sowmya Rangarajan; Abhishek Arun; David Thompson; Neelima Muralidharan (MTV, 2013)

State Retention Validation of C66X DSP Core. - Rama Venkatasubramanian; Oluleye Olorode; Abhishek Arun (MTV, 2013)

A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA. - Zoran Nikolic; Rama Venkatasubramanian; Jason A. T. Jones; Peter Labaziewicz (Hot Chips Symposium, 2015)

2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. - Rama Venkatasubramanian; Don Steiss; Greg Shurtz; Tim Anderson; Kai Chirca; Raghavendra Santhanagopal; Niraj Nandan; Anish Reghunath; Hetul Sanghvi; Daniel Wu; Abhijeet Chachad; Brian Karguth; et al. (ISSCC, 2020)