Addressing high frequency effects in VLSI interconnects with full wave model and CFH. - Ramachandra Achar; Michel S. Nakhla; Qi-Jun Zhang (ICCAD, 1995)

An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. - Guowu Zheng; Qi-Jun Zhang; Michel S. Nakhla; Ramachandra Achar (ICCAD, 1996)

Full-wave analysis of high-speed interconnects using complex frequency hopping. - Ramachandra Achar; Michel S. Nakhla; Qi-Jun Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Efficient simulation of on-chip RF components using model-reduction techniques. - Ramachandra Achar; Michel S. Nakhla (ISCAS (2), 1999)

Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques. - Pavan K. Gunupudi; Michel S. Nakhla; Ramachandra Achar (ISCAS (6), 1999)

Interconnect Modeling and Simulation. - Michel S. Nakhla; Ramachandra Achar (The VLSI Handbook, 1999)

Passive model order reduction of multiport distributed interconnects. - Emad Gad; Anestis Dounavis; Michel S. Nakhla; Ramachandra Achar (DAC, 2000)

Simulation of high-speed distributed interconnects using Krylov-space techniques. - Pavan K. Gunupudi; Michel S. Nakhla; Ramachandra Achar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations. - Anestis Dounavis; Ramachandra Achar; Michel S. Nakhla (ICECS, 2001)

Simulation of high-speed interconnects. - Ramachandra Achar; Michel S. Nakhla (Proc. IEEE, 2001)

Correction To "simulation of high-speed Interconnects". - Ramachandra Achar; Michel S. Nakhla (Proc. IEEE, 2001)

Passive closed-form time-domain macromodels for on-chip distributed RC interconnects. - Anestis Dounavis; Ramachandra Achar; Michel S. Nakhla (CICC, 2002)

Passive macromodeling of subnetworks characterized by measured data. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (ISCAS (3), 2003)

Fast sensitivity analysis of transmission line networks. - Natalie Nakhla; Anestis Dounavis; Ramachandra Achar; Michel S. Nakhla (ISCAS (5), 2004)

Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques. - Praveen Pai; Emad Gad; Ramachandra Achar; Roni Khazaka; Michel S. Nakhla (ISCAS (5), 2004)

Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. - Natalie Nakhla; Ramachandra Achar; Michel S. Nakhla; Anestis Dounavis (ASP-DAC, 2005)

Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. - Natalie Nakhla; Ramachandra Achar; Michel S. Nakhla (ISCAS (6), 2005)

On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (ISCAS (4), 2005)

Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (VLSI Design, 2005)

Passivity verification in delay-based macromodels of electrical interconnects. - Emad Gad; Changzhong Chen; Michel S. Nakhla; Ramachandra Achar (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (VLSI Design, 2006)

Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. - Gurpreet Shinh; Natalie Nakhla; Ramachandra Achar; Michel S. Nakhla; Ihsan Erdin (VLSI Design, 2006)

A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits. - Praveen Pai; Emad Gad; Ramachandra Achar; Michel S. Nakhla; Roni Khazaka (INFORMS J. Comput., 2006)

Sparse and passive reduction of massively coupled large multiport interconnects. - Natalie Nakhla; Michel S. Nakhla; Ramachandra Achar (ICCAD, 2007)

Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. - Changzhong Chen; Emad Gad; Natalie Nakhla; Ramachandra Achar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. - Dharmendra Saraswat; Ramachandra Achar; Michel S. Nakhla (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform. - Changzhong Chen; Dharmendra Saraswat; Ramachandra Achar; Emad Gad; Michel S. Nakhla; Mustapha Chérif-Eddine Yagoub (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations. - Emad Gad; Michel S. Nakhla; Ramachandra Achar; Yinghong Zhou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels. - Changzhong Chen; Dharmendra Saraswat; Ramachandra Achar; Emad Gad; Michel S. Nakhla; Mustapha Chérif-Eddine Yagoub (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures. - Nick Soveiko; Michel S. Nakhla; Ramachandra Achar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR). - Ramachandra Achar; Michel S. Nakhla; Harjot S. Dhindsa; Arvind R. Sridhar; Douglas Paul; Natalie Nakhla (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods. - Yinghong Zhou; Emad Gad; Michel S. Nakhla; Ramachandra Achar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Efficient parallel scheduler for circuit simulation exploiting binary link formulations. - Douglas Paul; Ramachandra Achar; Michel S. Nakhla; Natalie Nakhla (LASCAS, 2013)

Addressing Partitioning Issues in Parallel Circuit Simulation. - Douglas Paul; Ramachandra Achar; Michel S. Nakhla; Natalie Nakhla (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits. - Mina A. Farhan; Michel S. Nakhla; Emad Gad; Ramachandra Achar (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation. - Wai-Kong Lee; Ramachandra Achar; Michel S. Nakhla (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Fast Analysis of Time Interval Error in Current-Mode Drivers. - Jai Narayan Tripathi; Ramachandra Achar; Rakesh Malik (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures. - Ihsan Erdin; Ramachandra Achar (LASCAS, 2019)

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers. - Jai Narayan Tripathi; Muhammed Suhail Illikkal; Hitesh Shrimali; Ramachandra Achar (IEEE Access, 2019)

A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting. - Srinidhi Ganeshan; Naveen Kumar Elumalai; Ramachandra Achar (LASCAS, 2020)

An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications. - Wei Pau Kiat; Kai Ming Mok; Wai-Kong Lee; Hock Guan Goh; Ramachandra Achar (Microprocess. Microsystems, 2020)

DPCrypto: Acceleration of Post-quantum Cryptographic Algorithms using Dot-Product Instruction on GPUs. - Wai-Kong Lee; Hwajeong Seo; Seong Oun Hwang; Angshuman Karmakar; Jose Maria Bermudo Mera; Ramachandra Achar (IACR Cryptol. ePrint Arch., 2021)

GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation. - Wai-Kong Lee; Ramachandra Achar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters. - Muhammed Suhail Illikkal; Jai Narayan Tripathi; Vijender Kumar Sharma; Hitesh Shrimali; Ramachandra Achar (IEEE Access, 2022)

Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation. - Wai-Kong Lee; Ramachandra Achar (IEEE Access, 2022)

DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs. - Wai-Kong Lee; Hwajeong Seo; Seong Oun Hwang; Ramachandra Achar; Angshuman Karmakar; Jose Maria Bermudo Mera (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

PSIJ Transfer Function Response Prediction via NARNET and KBNNs. - Ahsan Javaid; Ramachandra Achar (NEWCAS, 2023)

Recognition of Electronic Component Orientations from Hand-Drawn Circuit Schematics through a Two Stage Machine Learning System. - Anuj Mathur; Ramachandra Achar (NewCAS, 2024)

cuTraNTT: A Novel Transposed Number Theoretic Transform Targeting Low Latency Homomorphic Encryption for IoT Applications. - Supriya Adhikary; Wai-Kong Lee; Angshuman Karmakar; Yongwoo Lee; Seong Oun Hwang; Ramachandra Achar (IACR Cryptol. ePrint Arch., 2024)