R. Sakthivel

According to our database, R. Sakthivel authored at least 16 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption.

I. Munavar Sheriff, R. Sakthivel

IEEE Access, 2024

2022

Mathematical and Circuit Level Analysis Interpretation and Recommendations on Neuron Models.

I. Munavar Sheriff, R. Sakthivel

J. Circuits Syst. Comput., 2022

Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations.

V. Keerthy Rai, R. Sakthivel

J. Circuits Syst. Comput., 2022

2021

VLSI System Architecture Optimization for DLMS Adaptive Filter using PPG based Multiplier.

Ramachandran Sakthivel, Premson Yohannan

Int. J. Syst. Syst. Eng., 2021

2020

Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications.

V. Keerthy Rai, R. Sakthivel

J. Circuits Syst. Comput., 2020

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, .

Thirumalesu Kudithi, R. Sakthivel

Int. J. Circuit Theory Appl., 2020

Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging.

Sreejeesh S. G., R. Sakthivel, Jayaraj U. Kidav

IEEE Access, 2020

2019

High-performance ECC processor architecture design for IoT security applications.

Thirumalesu Kudithi, R. Sakthivel

J. Supercomput., 2019

Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems.

Kishore Sanapala, Ramachandran Sakthivel

IET Circuits Devices Syst., 2019

2018

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications.

Kishore Sanapala, Ramachandran Sakthivel, Sang-Soo Yeo

J. Supercomput., 2018

High Performance GCM Architecture for the Security of High Speed Network.

Vanitha Mohanraj, Ramachandran Sakthivel, Anand Paul, Seungmin Rho

Int. J. Parallel Program., 2018

Nonlinear System Modelling Using Programmable Hardware for Soft Computing Applications.

M. Vanitha, R. Sakthivel, Mangayarkarasi Ramaiah, Suvarcha Sharma

Proceedings of the Soft Computing for Problem Solving, 2018

2014

Low power high throughput reconfigurable stream cipher hardware VLSI architectures.

R. Sakthivel, M. Vanitha, Harish M. Kittur

Int. J. Inf. Comput. Secur., 2014

Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy.

R. Sakthivel, Harish M. Kittur

Circuits Syst. Signal Process., 2014

2013

Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver.

R. Sakthivel, Harish M. Kittur

IEICE Electron. Express, 2013

2012

Low power energy efficient pipelined multiply-accumulate architecture.

R. Sakthivel, K. Sravanthi, Harish M. Kittur

Proceedings of the 2012 International Conference on Advances in Computing, 2012