Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits. - Saraju P. Mohanty; Ramakrishna Velagapudi; Valmiki Mukherjee; Hao Li (ISVLSI, 2005)

Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits. - Saraju P. Mohanty; Ramakrishna Velagapudi; Elias Kougianos (DATE, 2006)

Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis. - Saraju P. Mohanty; Elias Kougianos; Ramakrishna Velagapudi; Valmiki Mukherjee (ISCAS, 2006)

Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. - Saraju P. Mohanty; Ramakrishna Velagapudi; Elias Kougianos (ISQED, 2006)