Common Ada bindings to compartmented mode workstations. - C. Armstrong; R. Venkatraman (WADAS, 1994)

An evolutionary approach to timing driven FPGA placement. - R. Venkatraman; Lalit M. Patnaik (ACM Great Lakes Symposium on VLSI, 2000)

Rule-based system application for a technical problem in inventory issue. - R. Venkatraman; S. Venkatraman (Artif. Intell. Eng., 2000)

Soft-switching single-stage AC-to-DC converter with low harmonic distortion. - Ramakrishnan Venkatraman; Ashoka K. S. Bhat; Mark Edmunds (IEEE Trans. Aerosp. Electron. Syst., 2000)

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. - Karanth Shankaranarayana; Soujanna Sarkar; R. Venkatraman; Shyam S. Jagini; N. Venkatesh; Jagdish C. Rao; H. Udayakumar; M. Sambandam; K. P. Sheshadri; S. Talapatra; Parag Mhatre; Jais Abraham; et al. (ASP-DAC/VLSI Design, 2002)

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. - F. Duan; R. Castagnetti; R. Venkatraman; O. Kobozeva; S. Ramesh 004 (ISQED, 2003)

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. - Ruggero Castagnetti; R. Venkatraman; Brandon Bartz; Carl Monzel; T. Briscoe; Andres Teene; S. Ramesh 004 (ISQED, 2005)

A Soft-Switched Full-Bridge Single-Stage AC-to-DC Converter With Low-Line-Current Harmonic Distortion. - Ashoka K. S. Bhat; Ramakrishnan Venkatraman (IEEE Trans. Ind. Electron., 2005)

Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. - Bhaskar J. Karmakar; V. Kalyana Chakravarty; R. Venkatraman; Jagdish C. Rao (ISQED, 2006)

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. - R. Venkatraman; R. Castagnetti; S. Ramesh 004 (ISQED, 2006)

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. - R. Venkatraman; R. Castagnetti; Andres Teene; Benjamin Mbouombouo; S. Ramesh 004 (ISQED, 2009)

Early clock prototyping for design analysis and quality entitlement. - Ramamurthy Vishweshwara; Ramakrishnan Venkatraman; Vipul Kadodwala (ISQED, 2009)

Optimization strategies to improve statistical timing. - Parimala Viswanath; Pranav Murthy; Debajit Das; R. Venkatraman; Ajoy Mandal; Arvind Veeravalli; H. Udayakumar (ISQED, 2009)

Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. - R. Venkatraman; Shrikrishna Pundoor; Arun Koithyar; Madhusudan Rao; Jagdish C. Rao (VLSI Design, 2009)

An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. - Ramamurthy Vishweshwara; Ramakrishnan Venkatraman; H. Udayakumar; N. V. Arvind (VLSI Design, 2009)

DFM: Impact analysis in a high performance design. - S. M. Stalin; Amit Brahme; Ramakrishnan Venkatraman; Ajoy Mandal (ISQED, 2011)

Ensuring On-Die Power Supply Robustness in High-Performance Designs. - Sreekanth Soman; Amit Brahme; Ramakrishnan Venkatraman; Raashid Shaikh; Santhosh Thiyagaraja; Mahendrasing Patil (VLSI Design, 2011)

Placement aware clock gate cloning and redistribution methodology. - Ramamurthy Vishweshwara; Mahita Nagabhiru; Ramakrishnan Venkatraman (ISQED, 2012)

A Silicon Testing Strategy for Pulse-Width Failures. - Srinivas Vooka; Khushboo Agarwal; Abhijeet Shrivastava; Pranav Murthy; Ramakrishnan Venkatraman (VLSI Design, 2012)

Dynamic Co-Simulation Methods for Combined Transmission-Distribution System and Integration Time Step Impact on Convergence. - Ramakrishnan Venkatraman; Siddhartha Kumar Khaitan; Venkataramana Ajjarapu (CoRR, 2018)

Accurate Representation of Distribution System Dynamics in Bulk System Studies by Clusters of Composite Load Models. - Amarsagar Reddy Ramapuram Matavalam; R. Venkatraman; Venkataramana Ajjarapu (IAS, 2023)

Gateways for Institutional-Grade Commerce and Interoperability of Digital Assets. - Rafael Belchior; Thomas Hardjono; Alexandru Chiriac; Ramakrishnan Venkatraman (CoRR, 2025)