A technology independent MOS multiplier generator. - Kung-Chao Chu; Ramautar Sharma (DAC, 1984)

Architecture Design of a High-Quality Speech Synthesizer Based on the Multipulse LPC Technique. - Ramautar Sharma (IEEE J. Sel. Areas Commun., 1985)

Area-time efficient arithmetic elements for VLSI systems. - Ramautar Sharma (IEEE Symposium on Computer Arithmetic, 1987)

An AND-OR Parallel Execution System for Logic Program Evaluation. - Nam Sung Woo; Ramautar Sharma (ICPP, 1987)

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology. - Ramautar Sharma; Alexander D. Lopez; John A. Michejda; Steven J. Hillenius; John M. Andrews; Arnold J. Studwell (IEEE J. Solid State Circuits, 1989)