CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. - Thomas Wecker; Ramayya Kumar; Wolfgang Rosenstiel; Heinrich Krämer; Michael Neher (Inform. Forsch. Entwickl., 1989)

Automating Most Parts of Hardware Proofs in HOL. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (CAV, 1991)

Verification of synthesized circuits at register transfer level with flow graphs. - Fridtjof Feldbusch; Ramayya Kumar (EURO-DAC, 1991)

Integrating a First-Order Automatic Prover in the HOL Environment. - Ramayya Kumar; Thomas Kropf; Klaus Schneider 001 (TPHOLs, 1991)

First Steps Towards Automating Hardware Proofs in HOL. - Ramayya Kumar; Thomas Kropf; Klaus Schneider 001 (TPHOLs, 1991)

Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (VLSI, 1991)

The FAUST - Prover. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (CADE, 1992)

Efficient Representation and Computation of Tableau Proofs. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (TPHOLs, 1992)

Modelling Generic Hardware Structures by Abstract Datatypes. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (TPHOLs, 1992)

Embedding Hardware Verification Within a Commercial Design Framework. - Thomas Kropf; Ramayya Kumar; Klaus Schneider 001 (CHARME, 1993)

Hardware-Verification using First Order BDDs. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (CHDL, 1993)

Towards a Methodology for the Formal Hierarchical Verification. - Sofiène Tahar; Ramayya Kumar (ICCD, 1993)

A Functional Approach for Formalizing Regular Hardware Structures. - Dirk Eisenbiegler; Klaus Schneider 001; Ramayya Kumar (HUG, 1993)

Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (HUG, 1993)

Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (HUG, 1993)

Implementing a Methodology for Formally Verifying RISC Processors in HOL. - Sofiène Tahar; Ramayya Kumar (HUG, 1993)

Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. - Ramayya Kumar; Klaus Schneider 001; Thomas Kropf (Formal Methods Syst. Des., 1993)

Formal verification of pipeline conflicts in RISC processors. - Ramayya Kumar; Sofiène Tahar (EURO-DAC, 1994)

Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. - Klaus Schneider 001; Thomas Kropf; Ramayya Kumar (EDAC-ETC-EUROASIC, 1994)

A Formal Framework for High Level Synthesis. - Thomas Kropf; Klaus Schneider 001; Ramayya Kumar (TPCD, 1994)

Automating Verification by Functional Abstraction at the System Level. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (TPHOLs, 1994)

Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. - Sofiène Tahar; Ramayya Kumar (TPHOLs, 1994)

Accelerating Tableaux Proofs Using Compact Representations. - Klaus Schneider 001; Ramayya Kumar; Thomas Kropf (Formal Methods Syst. Des., 1994)

Formally embedding existing high level synthesis algorithms. - Dirk Eisenbiegler; Ramayya Kumar (CHARME, 1995)

Generic design flows for project management in a framework environment. - Ewa Kwee-Christoph; Fridtjof Feldbusch; Ramayya Kumar; Arno Kunzmann (ED&TC, 1995)

An Automata Theory Dedicated towards Formal Circuit Synthesis. - Dirk Eisenbiegler; Ramayya Kumar (TPHOLs, 1995)

Formal synthesis of circuits with a simple handshake protocol. - Ramayya Kumar; Thomas Kropf; Klaus Schneider 001 (VLSI Design, 1995)

Formal Specification and Verification Techniques for RISC Pipeline Conflicts. - Sofiène Tahar; Ramayya Kumar (Comput. J., 1995)

Formal Synthesis in Circuit Design - A Classification and Survey. - Ramayya Kumar; Christian Blumenröhr; Dirk Eisenbiegler; Detlef Schmid (FMCAD, 1996)

Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. - Dirk Eisenbiegler; Christian Blumenröhr; Ramayya Kumar (TPHOLs, 1996)

A constructive approach towards correctness of synthesis-application within retiming. - Dirk Eisenbiegler; Ramayya Kumar; Christian Blumenröhr (ED&TC, 1997)

A Practical Methodology for the Formal Verification of RISC Processors. - Sofiène Tahar; Ramayya Kumar (Formal Methods Syst. Des., 1998)

Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? - Ramayya Kumar (VLSI Design, 1999)