A 670 ps, 64 bit dynamic low-power adder design. - Ramchan Woo; Se-Joong Lee; Hoi-Jun Yoo (ISCAS, 2000)

A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. - Kangmin Lee; Chi Weon Yoon; Ramchan Woo; Jeong-Hun Kook; Ja-Il Koo; Tae-Sung Jung; Hoi-Jun Yoo (ISCAS (5), 2001)

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. - Chi Weon Yoon; Ramchan Woo; Jeengheon Kook; Se-Joong Lee; Kangmin Lee; Hoi-Jun Yeo (IEEE J. Solid State Circuits, 2001)

Optimization of portable system architecture for real-time 3D graphics. - Ju-Ho Sohn; Ramchan Woo; Hoi-Jun Yoo (ISCAS (1), 2002)

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. - Se-Jeong Park; Jeong-Su Kim; Ramchan Woo; Se-Joong Lee; Kang-Min Lee; Tae-Hum Yang; Jin-Yong Jung; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2002)

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. - Ramchan Woo; Chi Weon Yoon; Jeonghoon Kook; Se-Joong Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2002)

A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals. - Ramchan Woo; Sungdae Choi; Ju-Ho Sohn; Seong-Jun Song; Hoi-Jun Yoo (ESSCIRC, 2003)

A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. - Ramchan Woo; Sungdae Choi; Ju-Ho Sohn; Seong-Jun Song; Young-Don Bae; Hoi-Jun Yoo (ASP-DAC, 2004)

A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications. - Ju-Ho Sohn; Ramchan Woo; Hoi-Jun Yoo (Graphics Hardware, 2004)

3D graphics circuits for 3G multimedia terminals. - Ramchan Woo (SoC, 2004)

A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals. - Ramchan Woo; Sungdae Choi; Ju-Ho Sohn; Seong-Jun Song; Young-Don Bae; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2004)

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. - Ramchan Woo; Sungdae Choi; Ju-Ho Sohn; Seong-Jun Song; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2004)

A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications. - Ju-Ho Sohn; Jeong-Ho Woo; Ramchan Woo; Hoi-Jun Yoo (ESSCIRC, 2005)

Low-power 3D graphics processors for mobile terminals. - Ju-Ho Sohn; Yong-Ha Park; Chi Weon Yoon; Ramchan Woo; Se-Jeong Park; Hoi-Jun Yoo (IEEE Commun. Mag., 2005)

A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. - Ju-Ho Sohn; Jeong-Ho Woo; Min-wuk Lee; Hyejung Kim; Ramchan Woo; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2006)

High-speed image sensor technologies. - Johannes Solhusvik; Jung-Chak Ahn; Jan T. Bosiers; Boyd Fowler; Makoto Ikeda; Shoji Kawahito; Jerry Lin; Dan McGrath; Katsu Nakamura; Jun Ohta; Ramchan Woo (ISSCC, 2010)