A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock. - Ramen Dutta; T. K. Bhattacharyya (VLSI Design, 2009)

Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. - Ramen Dutta; Tarun Kanti Bhattacharyya; Xiang Gao 002; Eric A. M. Klumperink (VLSI Design, 2010)

Choosing Optimum Noise Figure and Data Rate in Wireless Sensor Network Radio Transceivers. - Ramen Dutta; Ronan A. R. van der Zee; Mark J. Bentum; André B. J. Kokkeler (ICC, 2011)

Jitter-Power minimization of digital frequency synthesis architectures. - Eric A. M. Klumperink; Ramen Dutta; Zhiyu Ru; Bram Nauta; Xiang Gao 002 (ISCAS, 2011)

Performance of chirped-FSK and chirped-PSK in the presence of partial-band interference. - Ramen Dutta; André B. J. Kokkeler; Ronan A. R. van der Zee; Mark J. Bentum (SCVT, 2011)

Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic. - Ramen Dutta; Eric A. M. Klumperink; Xiang Gao 002; Zhiyu Ru; Ronan A. R. van der Zee; Bram Nauta (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

An Ultra Low Energy FSK Receiver With In-Band Interference Robustness Exploiting a Three-Phase Chirped LO. - Ramen Dutta; Ronan A. R. van der Zee; André B. J. Kokkeler; Mark J. Bentum; Eric A. M. Klumperink; Bram Nauta (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)