Deterministic seed selection and pattern reduction in Logic BIST. - Ramesh Bhakthavatchalu; Sreeja Krishnan; V. Vineeth; M. Nirmala Devi 001 (VDAT, 2014)

Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time. - Patare Snehal Dilip; Geethu Remadevi Somanathan; Ramesh Bhakthavatchalu (ISED, 2019)

Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes. - Senthil Murugan; Ramesh Bhakthavatchalu; Karthi Balasubramanian; B. Yamuna; Deepak Mishra; Sree Ranjani Rajendran (IEEE Access, 2025)