Identifying Redundant Path Delay Faults in Sequential Circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (VLSI Design, 1996)

Test generation for primitive path delay faults in combinational circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCAD, 1997)

Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCD, 1997)

Delay Testing with Clock Control: An Alternative to Enhanced Scan. - Ramesh C. Tekumalla; Premachandran R. Menon (ITC, 1997)

On primitive fault test generation in non-scan sequential circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (ICCAD, 1998)

Robust testability of primitive faults using test points. - Ramesh C. Tekumalla; Premachandran R. Menon (ITC, 1999)

On Test Set Generation for Efficient Path Delay Fault Diagnosis. - Ramesh C. Tekumalla (VTS, 2000)

On Redundant Path Delay Faults in Synchronous Sequential Circuits. - Ramesh C. Tekumalla; Premachandran R. Menon (IEEE Trans. Computers, 2000)

On Diagnosing Path Delay Faults in an At-Speed Environment. - Ramesh C. Tekumalla; Srikanth Venkataraman; Jayabrata Ghosh-Dastidar (VTS, 2001)

Identification of primitive faults in combinational and sequentialcircuits. - Ramesh C. Tekumalla; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. - Ramesh C. Tekumalla; Scott Davidson 001 (ITC, 2002)

On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. - Ramesh C. Tekumalla (ITC, 2003)

An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. - Ramesh C. Tekumalla (VLSI Design, 2006)

Power aware transformation of bandlimited signals. - Prakash Krishnamoorthy; Ramesh C. Tekumalla (SoCC, 2013)

Quotient prediction for low power division. - Prakash Krishnamoorthy; Ramesh C. Tekumalla (SoCC, 2013)

Innovative practices session 2C: Memory test. - Charutosh Dixit; Ramesh C. Tekumalla; Sreejit Chakravarty; Manuel d'Abreu; Zhuoyu Bao; Concetta Riccobene (VTS, 2013)

On Handling Memory Scan Chains. - Surbhi Bansal; Aviansh Mendhalkar; Ramesh C. Tekumalla (NATW, 2014)

Local Repair Signature Handling for Repairable Memories. - Ramesh C. Tekumalla; Prakash Krishnamoorthy (NATW, 2014)

On-chip Clock Testing and Frequency Measurement. - Ramesh C. Tekumalla; Prakash Krishnamoorthy (NATW, 2014)

Innovative practices session 1C: Existing/emerging low power techniques. - Charutosh Dixit; Ramesh C. Tekumalla; Wei Zhao; Nilanjan Mukherjee 001; Vivek Chickermane (VTS, 2014)

Clock Domain Imbalances and Their Impact on Test Architecture. - Ramesh C. Tekumalla (NATW, 2015)

Innovative practices on memory test practice. - M. Casarsa; Gurgen Harutyunyan; Kaitlyn Chen; Ramesh Sharma; Giri Podichetty; Martin Keim; Sreejit Chakravarty; Ramesh C. Tekumalla (VTS, 2018)