Testing for Timing Faults in Synchronous Sequential Integrated Circuits. - Yashwant K. Malaiya; Ramesh Narayanaswamy (ITC, 1983)

Modeling and Testing for Timing Faults in Synchronous Sequential Circuits. - Yashwant K. Malaiya; Ramesh Narayanaswamy (IEEE Des. Test, 1984)

Panel: Your Core - My Problem? Integration and Verification of IP. - Gabe Moretti; Tim Hopes; Ramesh Narayanaswamy; Nanette Collins; Dave Kelf; Tom Anderson; Janick Bergeron; Ashish Dixit; Peter Flake (DAC, 2001)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines. - Jitendra Bhandari; Johann Knechtel; Ramesh Narayanaswamy; Siddharth Garg; Ramesh Karri (CoRR, 2024)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code. - Raghu Vamshi Hemadri; Jitendra Bhandari; Andre Nakkab; Johann Knechtel; Badri P. Gopalan; Ramesh Narayanaswamy; Ramesh Karri; Siddharth Garg (CoRR, 2025)