80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. - Janakiraman Viraraghavan; Derek Leu; Balaji Jayaraman; Alberto Cestero; Robert Kilker; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; et al. (VLSI Circuits, 2016)

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity. - Balaji Jayaraman; Derek Leu; Janakiraman Viraraghavan; Alberto Cestero; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; Toshiaki Kirihata; et al. (IEEE J. Solid State Circuits, 2018)

Optimized building extraction from high-resolution satellite imagery using deep learning. - Ramesh Raghavan; Dinesh Chander Verma; Digvijay Pandey; Rohit Anand; Binay Kumar Pandey; Harinder Singh (Multim. Tools Appl., 2022)