Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (VLSI Design, 2009)

Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (IET Circuits Devices Syst., 2010)

Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (J. Low Power Electron., 2010)

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (Microelectron. J., 2010)

Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (ISVLSI, 2011)

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. - Ramesh Vaddi; R. P. Agarwal; Sudeb Dasgupta (Microelectron. J., 2011)

Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier. - Huichu Liu; Ramesh Vaddi; Suman Datta; Vijaykrishnan Narayanan (ISLPED, 2013)

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency. - Kasturi Subramanyam; Sadulla Shaik; Ramesh Vaddi (VDAT, 2014)

Tunnel FET RF Rectifier Design for Energy Harvesting Applications. - Huichu Liu; Xueqing Li 002; Ramesh Vaddi; Kaisheng Ma; Suman Datta; Vijaykrishnan Narayanan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing. - Sadulla Shaik; Kalva Sri Rama Krishna; Ramesh Vaddi (VLSID, 2016)

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. - Aditya Japa; Harshita Vallabhaneni; Ramesh Vaddi (IET Circuits Devices Syst., 2016)

Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms. - Aditya Japa; T. Nagateja; Ramesh Vaddi (iNIS, 2017)

Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs. - T. Nagateja; Ramesh Vaddi (ISOCC, 2017)

A low voltage capacitor based current controlled sense amplifier for input offset compensation. - Y. Sudha Vani; N. Usha Rani; Ramesh Vaddi (ISOCC, 2017)

Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. - Aditya Japa; Harshita Vallabhaneni; Ramesh Vaddi (VDAT, 2017)

Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics. - Y. Sudha Vani; N. Usha Rani; Ramesh Vaddi (VDAT, 2017)

Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. - Aditya Japa; T. Nagateja; Santosh Kumar Vishvakarma; Yellappa Palagani; Jun Rim Choi; Ramesh Vaddi (ISCAS, 2018)

A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier. - Gauri Punekar; Venkateswarlu Gonuguntla; Yellappa Palagani; Jun Rim Choi; Ramesh Vaddi (ISOCC, 2018)

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD. - Sadulla Shaik; Kalva Sri Rama Krishna; Ramesh Vaddi (J. Circuits Syst. Comput., 2018)

Multi-objective Precision Optimization of Deep Neural Networks for Edge Devices. - Nhut-Minh Ho; Ramesh Vaddi; Weng-Fai Wong (DATE, 2019)

Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (IET Circuits Devices Syst., 2019)

A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. - Aditya Japa; Yellappa Palagani; Venkateswarlu Gonuguntla; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Jun Rim Choi; Ramesh Vaddi (ISCAS, 2020)

Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (IET Circuits Devices Syst., 2020)

Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (Int. J. Circuit Theory Appl., 2020)

Steep Switching NCFET based Logic for Future Energy Efficient Electronics. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2021)

Design and Analysis of 4-bit and 5-bit Flash ADC's in 90nm CMOS Technology for Energy Efficient IoT Applications. - Varanasi Koundinya; Madanu Karun Chand; Dharmavarapu Dhushyanth; Devarajugattu Jayanth Saikumar; Arumalla Varun Sai; Venu Birudu; Ramesh Vaddi (iSES, 2021)

Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators. - P. L. Lahari; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2021)

Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. - Aditya Japa; Manoj Kumar Majumder; Subhendu Kumar Sahoo; Ramesh Vaddi (Int. J. Circuit Theory Appl., 2021)

Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. - Venu Birudu; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2022)

Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19. - Santosh Kumar 006; Rishab Nagar; Saumya Bhatnagar; Ramesh Vaddi; Sachin Kumar Gupta; Mamoon Rashid 001; Ali Kashif Bashir; Tamim Alkhalifah (Comput. Electr. Eng., 2022)

Negative capacitance FETs for energy efficient and hardware secure logic designs. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2022)

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2023)

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks. - Venu Birudu; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2023)

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. - Venu Birudu; Tirumalarao Kadiyam; Koteswararao Penumalli; Aditya Japa; Sushma Nirmala Sambatur; Chongyan Gu; Siva Sankar Yellampalli; Ramesh Vaddi (ISCAS, 2024)

Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs. - Vinod Kumar Ancha; Fadi N. Sibai; Venkateswarlu Gonuguntla; Ramesh Vaddi (IEEE Access, 2024)