Verilog Coding Style for Efficient Synthesis In FPGA. - Himanshu Thapliyal; M. B. Srinivas; Rameshwar Rao 001; Hamid R. Arabnia (CDES, 2005)

A New Hardware Routing Accelerator for Multi-Terminal Nets. - Kaleem Fatima; Rameshwar Rao 001 (VLSI Design, 2009)

Segmentation of Oil Spill Images With Illumination-Reflectance Based Adaptive Level Set Model. - Raghotham Reddy Ganta; Syed Zaheeruddin; Narsimha Baddiri; R. Rameshwar Rao (IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2012)

Application of ASIP in Embedded Design with Optimized Clock Management. - Mood Venkanna; Rameshwar Rao 001; P. Chandra Sekhar (ICITKM, 2017)

Robust Maximum Likelihood Algorithm-based Mitigation technique for impulsive noise in MIMO-OFDM systems. - Sakimalla Prabhakar Girija; R. Rameshwar Rao (IEEE ANTS, 2020)

Robust Adaptive AutoRegressive Weighted Constant Modulus Algorithm for Blind Equalization in MIMO-OFDM System. - S. P. Girija; Rameshwar Rao 001 (ICICT, 2020)

Design of filter for image de-noising using discrete wavelet transform for ASIP. - Mood Venkanna; Rameshwar Rao 001; P. Chandra Sekhar (Int. J. Comput. Vis. Robotics, 2021)