A novel low power and high speed double edge explicit pulse triggered level converter flip-flop. - Ramin Razmdideh; Mohsen Saneei (Int. J. Circuit Theory Appl., 2015)

Two novel low power and very high speed pulse triggered flip-flops. - Ramin Razmdideh; Mohsen Saneei (Int. J. Circuit Theory Appl., 2015)

New Design of Scan Flip-Flop to Increase Speed and Reduce Power Consumption. - Ramin Razmdideh; Ali Mahani 001; Mohsen Saneei (J. Circuits Syst. Comput., 2015)

Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology. - Ramin Razmdideh; Mohsen Saneei (Int. J. Circuit Theory Appl., 2018)

All-digital delay line-based time difference amplifier in 65 nm CMOS technology. - Ramin Razmdideh; Mohsen Saneei (IET Circuits Devices Syst., 2019)