Implementing a family of high performance, micrograined architectures. - Robert Michael Owens; Mary Jane Irwin; Thomas P. Kelliher; Mohan Vishwanath; Raminder Singh Bajwa (ASAP, 1992)

Image Processing with the MGAP: A Cost Effective Solution. - Raminder Singh Bajwa; Robert Michael Owens; Mary Jane Irwin (IPPS, 1993)

A Massively Parallel, Micro-Grained VLSI Architecture. - Raminder Singh Bajwa; Robert Michael Owens; Mary Jane Irwin (VLSI Design, 1993)

The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. - Robert Michael Owens; Thomas P. Kelliher; Mary Jane Irwin; Mohan Vishwanath; Raminder Singh Bajwa; Wen-Lin Yang (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Rapid prototyping with programmable control paths. - Raminder Singh Bajwa; Chetana N. Keltcher; Paul Keltcher; Mary Jane Irwin (ASAP, 1994)

A SIMD solution to the sequence comparison problem on the MGAP. - Manjit Borah; Raminder Singh Bajwa; Sridhar Hannenhalli; Mary Jane Irwin (ASAP, 1994)

Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. - Raminder Singh Bajwa; Robert Michael Owens; Mary Jane Irwin (IEEE Trans. Computers, 1994)

Reducing the number of counters needed for integer multiplication. - Robert Michael Owens; Raminder Singh Bajwa; Mary Jane Irwin (IEEE Symposium on Computer Arithmetic, 1995)

The MGAP's programming environment and the *C++ language. - Raminder Singh Bajwa; Robert Michael Owens; Mary Jane Irwin (ASAP, 1995)

Simultaneous speech segmentation and phoneme recognition using dynamic programming. - Raminder Singh Bajwa; Robert Michael Owens; Thomas P. Kelliher (ICASSP, 1996)

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. - Mitsuru Hiraki; Raminder Singh Bajwa; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Katsuro Sasaki; Koichi Seki (ISLPED, 1996)

Mixed-autonomy local interconnect for reconfigurable SIMD arrays. - Raminder Singh Bajwa; Robert Michael Owens; Mary Jane Irwin (HiPC, 1997)

Instruction buffering to reduce power in processors for signal processing. - Raminder Singh Bajwa; Mitsuru Hiraki; Hirotsugu Kojima; Douglas J. Gorny; Ken-ichi Nitta; Avadhani Shridhar; Koichi Seki; Katsuro Sasaki (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Validation of an Architectural Level Power Analysis Technique. - Rita Yu Chen; Robert Michael Owens; Mary Jane Irwin; Raminder Singh Bajwa (DAC, 1998)

Comparative analysis of latches and flip-flops for high-performance systems. - Vladimir Stojanovic; Vojin G. Oklobdzija; Raminder Singh Bajwa (ICCD, 1998)

A unified approach in the analysis of latches and flip-flops for low-power systems. - Vladimir Stojanovic; Vojin G. Oklobdzija; Raminder Singh Bajwa (ISLPED, 1998)

Architecture-level power estimation and design experiments. - Rita Yu Chen; Mary Jane Irwin; Raminder Singh Bajwa (ACM Trans. Design Autom. Electr. Syst., 2001)