Improving speed and power characteristics of pulse-triggered flip-flops. - Marco Lanuzza; Ramiro Taco (LASCAS, 2014)

Dynamic gate-level body biasing for subthreshold digital design. - Marco Lanuzza; Ramiro Taco; Domenico Albano (LASCAS, 2014)

Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. - Domenico Albano; Marco Lanuzza; Ramiro Taco; Felice Crupi (Int. J. Circuit Theory Appl., 2015)

Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. - Ramiro Taco; Marco Lanuzza; Domenico Albano (VLSI Design, 2015)

Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2016)

Evaluation of Dual Mode Logic in 28nm FD-SOI technology. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2017)

Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (ISCAS, 2019)

An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. - Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish (IEEE J. Solid State Circuits, 2019)

Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Leonid Yavits; Marco Lanuzza; Alexander Fish (ISCAS, 2020)

Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. - Ramiro Taco; Leonid Yavits; Netanel Shavit; Inbal Stanger; Marco Lanuzza; Alexander Fish (ISCAS, 2020)

Dual Mode Logic Address Decoder. - Leonid Yavits; Ramiro Taco; Netanel Shavit; Inbal Stanger; Alexander Fish (ISCAS, 2020)

Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications. - Esteban Garzón; Benjamin Zambrano; Tatiana Moposita; Ramiro Taco; Luis-Miguel Prócel; Lionel Trojman (LASCAS, 2020)

Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Marco Lanuzza; Alexander Fish (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. - Netanel Shavit; Inbal Stanger; Ramiro Taco; Marco Lanuzza; Alexander Fish (ISCAS, 2021)

Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. - Inbal Stanger; Netanel Shavit; Ramiro Taco; Marco Lanuzza; Alexander Fish (ISCAS, 2021)

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. - Ricardo Escobar; Luis-Miguel Prócel; Lionel Trojman; Marco Lanuzza; Ramiro Taco (LASCAS, 2021)

RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. - Lionel Trojman; David Rivadeneira; Marco Villegas; Eliana Acurio; Marco Lanuzza; Luis-Miguel Procel; Ramiro Taco (LASCAS, 2021)

Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. - Esteban Garzón; Ramiro Taco; Luis-Miguel Prócel; Lionel Trojman; Marco Lanuzza (LASCAS, 2022)

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells. - Ariana Musello; Santiago S. Pérez; Marco Villegas; Luis-Miguel Prócel; Ramiro Taco; Lionel Trojman (LASCAS, 2022)

DMTJ-Based Non-Volatile Ternary Content Addressable Memory for Energy-Efficient High-Performance Systems. - Kevin Vicuña; Luis-Miguel Prócel; Lionel Trojman; Ramiro Taco (LASCAS, 2022)

A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. - Yizhak Shifman; Inbal Stanger; Netanel Shavit; Ramiro Taco; Alexander Fish; Joseph Shor (IEEE J. Solid State Circuits, 2022)

Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages. - Santiago S. Pérez; Alessandro Bedoya; Luis-Miguel Prócel; Ramiro Taco (LASCAS, 2023)

Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow. - Netanel Shavit; Inbal Stanger; Ramiro Taco; Alexander Fish; Itamar Levi (IEEE Access, 2023)

XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. - Ariana Musello; Esteban Garzón; Marco Lanuzza; Luis-Miguel Prócel; Ramiro Taco (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Low Power, Energy Efficient and High Performance Triple Mode Logic for IoT Applications. - Netanel Shavit; Inbal Stanger; Ramiro Taco; Leonid Yavits; Alexander Fish (PRIME, 2024)

Designing Precharge-Free Energy-Efficient Content-Addressable Memories. - Ramiro Taco; Esteban Garzón; Robert Hanhan; Adam Teman; Leonid Yavits; Marco Lanuzza (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Non-Volatile Content-Addressable Memory For Energy-Efficient & High-Performance Search And Update Operations. - Alessandro Bedoya; Benjamin Zambrano; Ramiro Taco; Luis-Miguel Prócel; Marco Lanuzza; Esteban Garzón (ISCAS, 2025)

Low Matchline Voltage Swing Content-Addressable Memory Cell. - Cristhopher Mosquera; Ramiro Taco; Benjamin Zambrano; Luis-Miguel Procel; Esteban Garzón; Marco Lanuzza (ISCAS, 2025)

Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. - Ramiro Taco; Esteban Garzón; Adam Teman; Leonid Yavits; Marco Lanuzza (ISCAS, 2025)

Assessment of 2T2R Logic-in-Memory in a Cycle-to-Cycle Variation-Aware Simulation Environment. - Martín Gavilánez; Silvana Guitarra; Ramiro Taco (NewCAS, 2025)