Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders. - Ramkrishna Swamy; Stephen Bates; Tyler L. Brandon (ISCAS (5), 2005)

Parallel encoders for low-density parity-check convolutional codes. - Stephen Bates; Ramkrishna Swamy (ISCAS, 2006)

Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes. - Stephen Bates; Duncan G. Elliott; Ramkrishna Swamy (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder. - Ramkrishna Swamy; Stephen Bates; Tyler L. Brandon; Bruce F. Cockburn; Duncan G. Elliott; John C. Koob; Zhengang Chen (IEEE J. Solid State Circuits, 2007)

A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. - Tyler L. Brandon; John C. Koob; Leendert van den Berg; Zhengang Chen; Amirhossein Alimohammad 001; Ramkrishna Swamy; Jason Klaus; Stephen Bates; Vincent C. Gaudet; Bruce F. Cockburn; Duncan G. Elliott (ISCAS, 2008)

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes. - Tyler L. Brandon; John C. Koob; Leendert van den Berg; Zhengang Chen; Amirhossein Alimohammad 001; Ramkrishna Swamy; Jason Klaus; Stephen Bates; Vincent C. Gaudet; Bruce F. Cockburn; Duncan G. Elliott (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)