Implementing a fuzzy processor on programmable logic circuits: modularization criteria. - Esperanza M. López; Alfonso Aniorte Carbonell; Ramón Ruiz Merino (EUSFLAT-ESTYLF Joint Conf., 1999)

Automatic Recognition of Weld Regions in Radiographic Images of Welded Joints. - Rafael Vilar; Juan Zapata-Pérez; Luis Bernabé; Ramón Ruiz Merino (VIIP, 2001)

An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. - José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Hans Hauer; Ramón Ruiz Merino (IWANN (2), 2003)

Current Mode CMOS Synthesis of a Motor-Control Neural System. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Hans Hauer; José Ángel Díaz-Madrid (IWANN (2), 2003)

Description and Simulation of Bio-inspired Systems Using VHDL-AMS. - Ginés Doménech-Asensi; José-Alejandro López Alcantud; Ramón Ruiz Merino (IWINAC (2), 2005)

Detection of anomalous events in biomedical signals by wigner analysis and instant-wise Rényi entropy. - Salvador Gabarda; Gabriel Cristóbal; Juan Martínez-Alajarín; Ramón Ruiz Merino (EUSIPCO, 2006)

Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. - Ginés Doménech-Asensi; Juan Martínez-Alajarín; Ramón Ruiz Merino; José-Alejandro López Alcantud (FPL, 2006)

Compression system for the phonocardiographic signal. - F. Javier Toledo-Moreo; A. Legaz-Cano; J. Javier Martínez-Álvarez; Juan Martínez-Alajarín; Ramón Ruiz Merino (FPL, 2007)

Optimization of the Compression Parameters of a Phonocardiographic Telediagnosis System Using Genetic Algorithms. - Juan Martínez-Alajarín; F. Javier Garrigós-Guerrero; Ramón Ruiz Merino (IWINAC (1), 2007)

Classification and Diagnosis of Heart Sounds and Murmurs Using Artificial Neural Networks. - Juan Martínez-Alajarín; José López-Candel; Ramón Ruiz Merino (IWINAC (1), 2007)

Accurate and reusable macromodeling technique using a fuzzy-logic approach. - Ginés Doménech-Asensi; Juan Hinojosa; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2008)

Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. - José Ángel Díaz-Madrid; Harald Neubauer; Hans Hauer; Ginés Doménech-Asensi; Ramón Ruiz Merino (DATE, 2009)

Personal Notes about the Figure and Legate of Professor Mira. - Ramón Ruiz Merino (IWINAC (1), 2009)

A fourth order CMOS band pass filter for PIR sensors. - Ginés Doménech-Asensi; F. Martinez-Viviente; J. Illade-Quinteiro; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; Juan Martínez-Alajarín; Francisco J. Fernández-Luque; Juan M. Carrillo; Miguel Angel Domínguez (ICECS, 2012)

Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. - Ginés Doménech-Asensi; José Ángel Díaz-Madrid; Ramón Ruiz Merino (Int. J. Circuit Theory Appl., 2013)

Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. - Ricardo Carmona-Galán; Jorge Fernández-Berni; Ángel Rodríguez-Vázquez; Paula López Martinez 001; Víctor Manuel Brea Sánchez; Diego Cabello Ferrer; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez (ICDSC, 2018)

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. - Pablo Rubio-Ibáñez; Ramón Ruiz Merino; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; José Ángel Díaz-Madrid; José-Alejandro López Alcantud (Int. J. Circuit Theory Appl., 2018)

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Javier Martínez 001 (ISCAS, 2020)

All-hardware SIFT implementation for real-time VGA images feature extraction. - Ginés Doménech-Asensi; Juan Zapata-Pérez; Ramón Ruiz Merino; José-Alejandro López Alcantud; José Ángel Díaz-Madrid; Víctor Manuel Brea Sánchez; Paula López 001 (J. Real Time Image Process., 2020)

Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; J. Javier Martínez-Álvarez; Juan Zapata-Pérez; Ramón Ruiz Merino (Circuits Syst. Signal Process., 2021)

A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. - Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez; José Ángel Díaz-Madrid (ISCAS, 2023)

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. - José Ángel Díaz-Madrid; Ginés Doménech-Asensi; Ramón Ruiz Merino; Juan Zapata-Pérez (J. Real Time Image Process., 2024)

Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. - Ginés Doménech-Asensi; Francisco Javier Andreo-Oliver; Ramón Ruiz Merino; José Ángel Díaz-Madrid (ISCAS, 2025)