Optimization of phase-locked loop performance in data recovery systems. - Ramon S. Co; James H. Mulligan Jr. (IEEE J. Solid State Circuits, 1994)

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation. - Howard C. Yang; Lance K. Lee; Ramon S. Co (IEEE J. Solid State Circuits, 1997)