On the computation of criticality in statistical timing analysis. - S. Ramprasath 001; Vinita Vasudevan (ICCAD, 2012)

Statistical Criticality Computation Using the Circuit Delay. - S. Ramprasath 001; Vinita Vasudevan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

An efficient algorithm for statistical timing yield optimization. - S. Ramprasath 001; Vinita Vasudevan (DAC, 2015)

Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient. - Ramprasath S 001; Vinita Vasudevan (ACM Trans. Design Autom. Electr. Syst., 2016)

A Skew-Normal Canonical Model for Statistical Static Timing Analysis. - Ramprasath S 001; Madiwalar Vijaykumar; Vinita Vasudevan (IEEE Trans. Very Large Scale Integr. Syst., 2016)

GNNIE: GNN inference engine with load-balancing and graph-specific caching. - Sudipta Mondal; Susmita Dey Manasi; Kishor Kunal; Ramprasath S 001; Sachin S. Sapatnekar (DAC, 2022)

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. - Tonmoy Dhar; Ramprasath S 001; Jitesh Poojary; Soner Yaldiz; Steven M. Burns; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. - Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Ramprasath S 001; Kishor Kunal; Sachin S. Sapatnekar; Ramesh Harjani (ESSDERC, 2023)

A Multicore GNN Training Accelerator. - Sudipta Mondal; Ramprasath S 001; Ziqing Zeng; Kishor Kunal; Sachin S. Sapatnekar (ISLPED, 2023)

3SAT on an All-to-All-Connected CMOS Ising Solver Chip. - M. Hüsrev Cilasun; Ziqing Zeng; Ramprasath S 001; Abhimanyu Kumar; Hao Lo; William Cho; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. - Sudipta Mondal; Susmita Dey Manasi; Kishor Kunal; Ramprasath S 001; Ziqing Zeng; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Reinforcing the Connection between Analog Design and EDA (Invited Paper). - Kishor Kunal; Meghna Madhusudan; Jitesh Poojary; S. Ramprasath 001; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. - Kishor Kunal; Jitesh Poojary; S. Ramprasath 001; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Exact Computation of Error in Approximate Circuits using SAT and Message-Passing Algorithms. - S. Ramprasath 001; Marrivada Gopala Krishna Sai Charan; Vinita Vasudevan (CoRR, 2024)

COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. - Hüsrev Cilasun; William Moy; Ziqing Zeng; Tahmida Islam; Hao Lo; Alex Vanasse; Megan Tan; Mohammad Anees; Ramprasath S 001; Abhimanyu Kumar; Sachin S. Sapatnekar; Chris H. Kim; et al. (Zenodo, 2024)

DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design. - Abhimanyu Kumar; S. Ramprasath 001; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2025)