A low complexity modulo 2n+1 squarer design. - Ramya Muralidharan; Chip-Hong Chang; Ching-Chuen Jong (APCCAS, 2008)

Programmable LSB-first and MSB-first modular multipliers for ECC in GF(2m). - Ravi Kumar Satzoda; Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2008)

Fixed and Variable Multi-modulus Squarer Architectures for Triple Moduli base of RNS. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2009)

Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2010)

A simple radix-4 Booth encoded modulo 2n+1 multiplier. - Ramya Muralidharan; Chip-Hong Chang (ISCAS, 2011)

Radix-8 Booth Encoded Modulo 2 n -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers. - Ramya Muralidharan; Chip-Hong Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)