A Single-Relation Module for a Data Base Machine. - Bruce W. Arden; Ran Ginosar (ISCA, 1981)

MP/C: A Multiprocessor/Computer Architecture. - Bruce W. Arden; Ran Ginosar (IEEE Trans. Computers, 1982)

Performance evaluation of the MP/C. - Bruce W. Arden; Ran Ginosar (AFIPS National Computer Conference, 1983)

Design and Implementation of Switching Systems for Parallel Processors. - Ran Ginosar; Dwight D. Hill (ICPP, 1985)

Topological comparison of perfect shuffle and hypercube. - Ran Ginosar; David Egozi (Int. J. Parallel Program., 1989)

An efficient implementation of Boolean functions nd finite state machine as self-timed circuit. - Llana David; Ran Ginosar; Michael Yoeli (SIGARCH Comput. Archit. News, 1989)

An Extended RISC Methodology and its Application to FCP. - Arie Harsat; Ran Ginosar (ICLP, 1990)

Foveating vision systems architecture: image acquisition and display. - Yehoshua Y. Zeevi; Ran Ginosar (VCIP, 1990)

CARMEL-2: A second generation VLSI architecture for Flat Concurrent Prolog. - Arie Harsat; Ran Ginosar (New Gener. Comput., 1990)

On the potential of asynchronous pipelined processors. - Ran Ginosar; Nick Michell (SIGARCH Comput. Archit. News, 1990)

CARMEL-4: The Unify-Spawn Machine for FCP. - Arie Harsat; Ran Ginosar (ICLP, 1991)

An Efficient Implementation of Boolean Functions as Self-Timed Circuits. - Ilana David; Ran Ginosar; Michael Yoeli (IEEE Trans. Computers, 1992)

Implementing Sequential Machines as Self-Timed Circuits. - Ilana David; Ran Ginosar; Michael Yoeli (IEEE Trans. Computers, 1992)

Self-Timed Architecture of a Reduced Instruction Set Computer. - Ilana David; Ran Ginosar; Michael Yoeli (Asynchronous Design Methodologies, 1993)

Control unit synthesis from a high-level language. - Alan Rotman; Ran Ginosar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Adaptive sensitivity CCD image sensor. - Sarit Chen; Ran Ginosar (ICPR (3), 1994)

Spatio-chromatic model for colour image processing. - Stuart G. Wolf; Ran Ginosar; Yehoshua Y. Zeevi (ICPR (1), 1994)

Self-timed is self-checking. - Ilana David; Ran Ginosar; Michael Yoeli (J. Electron. Test., 1995)

Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. - Rakefet Kol; Ran Ginosar; Goel Samuel (ASYNC, 1996)

A Double-Latched Asynchronous Pipeline. - Rakefet Kol; Ran Ginosar (ICCD, 1997)

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. - Wei-Chun Chou; Peter A. Beerel; Ran Ginosar; Rakefet Kol; Chris J. Myers; Shai Rotem; Ken S. Stevens; Kenneth Y. Yun (ASYNC, 1998)

Adaptive synchronization. - Ran Ginosar; Rakefet Kol (ICCD, 1998)

Kin: A High Performance Asynchronous Processor Architecture. - Rakefet Kol; Ran Ginosar (International Conference on Supercomputing, 1998)

A low power video processor. - Uzi Zangi; Ran Ginosar (ISLPED, 1998)

Spatio-Chromatic Image Enhancement Based on a Model of Human Visual Information Processing. - Stuart G. Wolf; Ran Ginosar; Yehoshua Y. Zeevi (J. Vis. Commun. Image Represent., 1998)

RAPPID: An Asynchronous Instruction Length Decoder. - Shai Rotem; Ken S. Stevens; Charles Dike; Marly Roncken; Boris Agapiev; Ran Ginosar; Rakefet Kol; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun (ASYNC, 1999)

Relative Timing. - Ken S. Stevens; Shai Rotem; Ran Ginosar (ASYNC, 1999)

CAD Directions for High Performance Asynchronous Circuits. - Ken S. Stevens; Shai Rotem; Steven M. Burns; Jordi Cortadella; Ran Ginosar; Michael Kishinevsky; Marly Roncken (DAC, 1999)

A low-light-level sensor for medical diagnostic applications. - Yevgeny Perelman; Ran Ginosar (IEEE J. Solid State Circuits, 2001)

An asynchronous instruction length decoder. - Kenneth S. Stevens; Shai Rotem; Ran Ginosar; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun; Rakefet Kol; Charles Dike; Marly Roncken (IEEE J. Solid State Circuits, 2001)

Parallel VLSI architecture for MAP turbo decoder. - Rostislav (Reuven) Dobkin; Michael Peleg; Ran Ginosar (PIMRC, 2002)

Fourteen Ways to Fool Your Synchronizer. - Ran Ginosar (ASYNC, 2003)

Timing Measurements of Synchronization Circuits. - Yaron Semiat; Ran Ginosar (ASYNC, 2003)

A clock-tuning circuit for system-on-chip. - Y. Elboim; Avinoam Kolodny; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Relative timing [asynchronous design]. - Ken S. Stevens; Ran Ginosar; Shai Rotem (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Data Synchronization Issues in GALS SoCs. - Rostislav (Reuven) Dobkin; Ran Ginosar; Christos P. Sotiriou (ASYNC, 2004)

Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. - Alex Branover; Rakefet Kol; Ran Ginosar (DATE, 2004)

Automatic hardware-efficient SoC integration by QoS network on chip. - Evgeny Bolotin; Arkadiy Morgenshtein; Israel Cidon; Ran Ginosar; Avinoam Kolodny (ICECS, 2004)

Micro-modem - reliability solution for NoC communications. - Arkadiy Morgenshtein; Evgeny Bolotin; Israel Cidon; Avinoam Kolodny; Ran Ginosar (ICECS, 2004)

Low energy asynchronous adders. - Ilya Obridko; Ran Ginosar (ICECS, 2004)

Comparative analysis of serial vs parallel links in NoC. - Arkadiy Morgenshtein; Israel Cidon; Avinoam Kolodny; Ran Ginosar (SoC, 2004)

A Predictive Synchronizer for Periodic Clock Domains. - Uri Frank; Ran Ginosar (PATMOS, 2004)

Cost considerations in network on chip. - Evgeny Bolotin; Israel Cidon; Ran Ginosar; Avinoam Kolodny (Integr., 2004)

QNoC: QoS architecture and design process for network on chip. - Evgeny Bolotin; Israel Cidon; Ran Ginosar; Avinoam Kolodny (J. Syst. Archit., 2004)

Asynchronous gate-diffusion-input (GDI) circuits. - Arkadiy Morgenshtein; Michael Moreinis; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

An Asynchronous Router for Multiple Service Levels Networks on Chip. - Rostislav (Reuven) Dobkin; Victoria Vishnyakov; Eyal Friedman; Ran Ginosar (ASYNC, 2005)

Formal Verification of Synchronizers. - Tsachy Kapschitz; Ran Ginosar (CHARME, 2005)

Low-leakage repeaters for NoC interconnects. - Arkadiy Morgenshtein; Israel Cidon; Ran Ginosar; Avinoam Kolodny (ISCAS (1), 2005)

Low energy asynchronous architectures. - Ilya Obridko; Ran Ginosar (ISCAS (5), 2005)

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. - Rostislav (Reuven) Dobkin; Michael Peleg; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Fast Asynchronous Shift Register for Bit-Serial Communication. - Rostislav (Reuven) Dobkin; Ran Ginosar; Avinoam Kolodny (ASYNC, 2006)

Efficient link capacity and QoS design for network-on-chip. - Zvika Guz; Isask'har Walter; Evgeny Bolotin; Israel Cidon; Ran Ginosar; Avinoam Kolodny (DATE, 2006)

A predictive synchronizer for periodic clock domains. - Uri Frank; Tsachy Kapschitz; Ran Ginosar (Formal Methods Syst. Des., 2006)

A low-power inverted ladder D/a converter. - Yevgeny Perelman; Ran Ginosar (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

High Rate Data Synchronization in GALS SoCs. - Rostislav (Reuven) Dobkin; Ran Ginosar; Christos P. Sotiriou (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Minimal Energy Asynchronous Dynamic Adders. - Ilya Obridko; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2006)

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. - Rostislav (Reuven) Dobkin; Yevgeny Perelman; Tuvia Liran; Ran Ginosar; Avinoam Kolodny (ASYNC, 2007)

Routing table minimization for irregular mesh NoCs. - Evgeny Bolotin; Israel Cidon; Ran Ginosar; Avinoam Kolodny (DATE, 2007)

The Power of Priority: NoC Based Distributed Cache Coherency. - Evgeny Bolotin; Zvika Guz; Israel Cidon; Ran Ginosar; Avinoam Kolodny (NOCS, 2007)

QNoC Asynchronous Router with Dynamic Virtual Channel Allocation. - Rostislav (Reuven) Dobkin; Ran Ginosar; Israel Cidon (NOCS, 2007)

Access Regulation to Hot-Modules in Wormhole NoCs. - Isask'har Walter; Israel Cidon; Ran Ginosar; Avinoam Kolodny (NOCS, 2007)

An Integrated System for Multichannel Neuronal Recording With Spike/LFP Separation, Integrated A/D Conversion and Threshold Detection. - Yevgeny Perelman; Ran Ginosar (IEEE Trans. Biomed. Eng., 2007)

Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme. - Rami Rom; Jacob Erel; Michael Glikson; Randy A. Lieberman; Kobi Rosenblum; Ofer Binah; Ran Ginosar; David L. Hayes 001 (IEEE Trans. Neural Networks, 2007)

Network Delays and Link Capacities in Application-Specific Wormhole NoCs. - Zvika Guz; Isask'har Walter; Evgeny Bolotin; Israel Cidon; Ran Ginosar; Avinoam Kolodny (VLSI Design, 2007)

Fast Universal Synchronizers. - Rostislav (Reuven) Dobkin; Ran Ginosar (PATMOS, 2008)

Parallel vs. serial on-chip communication. - Rostislav (Reuven) Dobkin; Arkadiy Morgenshtein; Avinoam Kolodny; Ran Ginosar (SLIP, 2008)

Timing optimization in logic with interconnect. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (SLIP, 2008)

Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. - A. Elyada; Ran Ginosar; Uri C. Weiser (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Power efficient tree-based crosslinks for skew reduction. - Inna Vaisband; Ran Ginosar; Avinoam Kolodny; Eby G. Friedman (ACM Great Lakes Symposium on VLSI, 2009)

The Capacity Allocation Paradox. - Asaf Baron; Ran Ginosar; Isaac Keslassy (INFOCOM, 2009)

Multiple clock and voltage domains for chip multi processors. - Efraim Rotem; Avi Mendelson; Ran Ginosar; Uri C. Weiser (MICRO, 2009)

Two-phase synchronization with sub-cycle latency. - Rostislav (Reuven) Dobkin; Ran Ginosar (Integr., 2009)

QNoC asynchronous router. - Rostislav (Reuven) Dobkin; Ran Ginosar; Avinoam Kolodny (Integr., 2009)

The Devolution of Synchronizers. - Salomon Beer; Ran Ginosar; Michael Priel; Rostislav (Reuven) Dobkin; Avinoam Kolodny (ASYNC, 2010)

Timing-driven variation-aware nonuniform clock mesh synthesis. - Ameer Abdelhadi; Ran Ginosar; Avinoam Kolodny; Eby G. Friedman (ACM Great Lakes Symposium on VLSI, 2010)

Network-on-Chip Architectures for Neural Networks. - Dmitri Vainbrand; Ran Ginosar (NOCS, 2010)

Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. - Amit Berman; Ran Ginosar; Idit Keidar (VLSI-SoC, 2010)

Asynchronous Current Mode Serial Communication. - Rostislav (Reuven) Dobkin; Michael Moyal; Avinoam Kolodny; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. - Arkadiy Morgenshtein; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2010)

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm. - Salomon Beer; Ran Ginosar; Michael Priel; Rostislav (Reuven) Dobkin; Avinoam Kolodny (ISCAS, 2011)

Metastability and Synchronizers: A Tutorial. - Ran Ginosar (IEEE Des. Test Comput., 2011)

Scalable network-on-chip architecture for configurable neural networks. - Dmitri Vainbrand; Ran Ginosar (Microprocess. Microsystems, 2011)

Performance of a Hardware Scheduler for Many-core Architecture. - Itai Avron; Ran Ginosar (HPCC-ICESS, 2012)

Energy metrics for power efficient crosslink and mesh topologies. - Inna Vaisband; Eby G. Friedman; Ran Ginosar; Avinoam Kolodny (ISCAS, 2012)

An Extended Metastability Simulation Method for Synchronizer Characterization. - Salomon Beer; Ran Ginosar (PATMOS, 2012)

TCP Window Based DVFS for Low Power Network Controller SoC. - Eyal-Itzhak Nave; Ran Ginosar (PATMOS, 2012)

3D cache hierarchy optimization. - Leonid Yavits; Amir Morad; Ran Ginosar (3DIC, 2013)

MTBF Estimation in Coherent Clock Domains. - Salomon Beer; Ran Ginosar; Rostislav (Reuven) Dobkin; Yoav Weizman (ASYNC, 2013)

Metastability challenges for 65nm and beyond: simulation and measurements. - Salomon Beer; Ran Ginosar; Jerome Cox; Tom Chaney; David M. Zar (DATE, 2013)

PBD: packet buffer DVFs. - Eyal-Itzhak Nave; Ran Ginosar (ACM Great Lakes Symposium on VLSI, 2013)

The Effect of Communication and Synchronization on Amdahl Law in Multicore Systems. - Leonid Yavits; Amir Morad; Ran Ginosar (CoRR, 2013)

Thermal analysis of 3D associative processor. - Leonid Yavits; Amir Morad; Ran Ginosar (CoRR, 2013)

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. - Ameer Abdelhadi; Ran Ginosar; Avinoam Kolodny; Eby G. Friedman (Integr., 2013)

Metastability in Better-Than-Worst-Case Designs. - Salomon Beer; Marco Cannizzaro; Jordi Cortadella; Ran Ginosar; Luciano Lavagno (ASYNC, 2014)

Hardware Scheduler Performance on the Plural Many-Core Architecture. - Itai Avron; Ran Ginosar (MES@ISCA, 2014)

Efficient Dense and Sparse Matrix Multiplication on GP-SIMD. - Amir Morad; Leonid Yavits; Ran Ginosar (PATMOS, 2014)

Convex optimization of resource allocation in asymmetric and heterogeneous SoC. - Amir Morad; Leonid Yavits; Ran Ginosar (PATMOS, 2014)

Energy management of highly dynamic server workloads in an heterogeneous data center. - Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ahmad Yasin; Ran Ginosar (PATMOS, 2014)

Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. - Amir Morad; Tomer Y. Morad; Leonid Yavits; Ran Ginosar; Uri C. Weiser (IEEE Comput. Archit. Lett., 2014)

Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. - Efraim Rotem; Ran Ginosar; Uri C. Weiser; Avi Mendelson (IEEE Comput. Archit. Lett., 2014)

Cache Hierarchy Optimization. - Leonid Yavits; Amir Morad; Ran Ginosar (IEEE Comput. Archit. Lett., 2014)

StarSync: An extendable standard-cell mesochronous synchronizer. - Dmitry Verbitsky; Rostislav (Reuven) Dobkin; Ran Ginosar; Salomon Beer (Integr., 2014)

The effect of communication and synchronization on Amdahl's law in multicore systems. - Leonid Yavits; Amir Morad; Ran Ginosar (Parallel Comput., 2014)

Compiler-Directed Power Management for Superscalars. - Jawad Haj-Yihia; Yosi Ben-Asher; Efraim Rotem; Ahmad Yasin; Ran Ginosar (ACM Trans. Archit. Code Optim., 2014)

GP-SIMD Processing-in-Memory. - Amir Morad; Leonid Yavits; Ran Ginosar (ACM Trans. Archit. Code Optim., 2014)

Guest Editors' Introduction - Special Issue on Network-on-Chip. - Ran Ginosar; Karam S. Chatha (IEEE Trans. Computers, 2014)

Asynchronous sub-threshold ultra-low power processor. - Ron Diamant; Ran Ginosar; Christos P. Sotiriou (PATMOS, 2015)

Resistive Associative Processor. - Leonid Yavits; Shahar Kvatinsky; Amir Morad; Ran Ginosar (IEEE Comput. Archit. Lett., 2015)

Power and thermal constraints of modern system-on-a-chip computer. - Efraim Rotem; Ran Ginosar; Avi Mendelson; Uri C. Weiser (Microelectron. J., 2015)

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator. - Leonid Yavits; Amir Morad; Ran Ginosar (IEEE Trans. Computers, 2015)

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits. - Marco Cannizzaro; Salomon Beer; Jordi Cortadella; Ran Ginosar; Luciano Lavagno (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Sparse Matrix Multiplication On An Associative Processor. - Leonid Yavits; Amir Morad; Ran Ginosar (IEEE Trans. Parallel Distributed Syst., 2015)

Variability in Multistage Synchronizers. - Salomon Beer; Jerome Cox; Ran Ginosar; Tom Chaney; David M. Zar (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Eleven Ways to Boost Your Synchronizer. - Salomon Beer; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance. - Salomon Beer; Ran Ginosar (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Using Scan Side Channel for Detecting IP Theft. - Leonid Azriel; Ran Ginosar; Shay Gueron; Avi Mendelson (HASP@ISCA, 2016)

Deduplication in resistive content addressable memory based solid state drive. - Roman Kaplan; Leonid Yavits; Amir Morad; Ran Ginosar (PATMOS, 2016)

H-EARtH: Heterogeneous Multicore Platform Energy Management. - Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ran Ginosar; Eliezer Weissmann; Yoni Aizik (Computer, 2016)

Effect of Data Sharing on Private Cache Design in Chip Multiprocessors. - Leonid Yavits; Amir Morad; Ran Ginosar (CoRR, 2016)

Convex Optimization of Real Time SoC. - Leonid Yavits; Amir Morad; Ran Ginosar; Uri C. Weiser (CoRR, 2016)

Resistive GP-SIMD Processing-In-Memory. - Amir Morad; Leonid Yavits; Shahar Kvatinsky; Ran Ginosar (ACM Trans. Archit. Code Optim., 2016)

The Effect of Temperature on Amdahl Law in 3D Multicore Era. - Leonid Yavits; Amir Morad; Ran Ginosar (IEEE Trans. Computers, 2016)

Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering. - Leonid Azriel; Ran Ginosar; Avi Mendelson (ACM Great Lakes Symposium on VLSI, 2017)

Resistive Address Decoder. - Leonid Yavits; Uri C. Weiser; Ran Ginosar (IEEE Comput. Archit. Lett., 2017)

Sparse Matrix Multiplication on CAM Based Accelerator. - Leonid Yavits; Ran Ginosar (CoRR, 2017)

MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. - Leonid Yavits; Amir Morad; Uri C. Weiser; Ran Ginosar (CoRR, 2017)

A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. - Y. Zhang; Rostislav (Reuven) Dobkin; Aharon Unikovski; Danniel Nahmanny; Goel Samuel; Michael Moyal; Ran Ginosar (Integr., 2017)

A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. - Roman Kaplan; Leonid Yavits; Ran Ginosar; Uri C. Weiser (IEEE Micro, 2017)

From Processing-in-Memory to Processing-in-Storage. - Roman Kaplan; Leonid Yavits; Ran Ginosar (Supercomput. Front. Innov., 2017)

Using Scan Side Channel to Detect IP Theft. - Leonid Azriel; Ran Ginosar; Shay Gueron; Avi Mendelson (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Accelerator for Sparse Machine Learning. - Leonid Yavits; Ran Ginosar (IEEE Comput. Archit. Lett., 2018)

PRINS: Resistive CAM Processing in Storage. - Leonid Yavits; Roman Kaplan; Ran Ginosar (CoRR, 2018)

RASSA: Resistive Accelerator for Approximate Long Read DNA Mapping. - Roman Kaplan; Leonid Yavits; Ran Ginosar (CoRR, 2018)

Enabling Full Associativity with Memristive Address Decoder. - Leonid Yavits; Roman Kaplan; Ran Ginosar (IEEE Micro, 2018)

POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. - Roman Kaplan; Leonid Yavits; Ran Ginosar (PACT, 2019)

POSTER: GIRAF: General Purpose In-Storage Resistive Associative Framework. - Leonid Yavits; Roman Kaplan; Ran Ginosar (PACT, 2019)

SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. - Leonid Azriel; Ran Ginosar; Avi Mendelson (ASHES@CCS, 2019)

AIDA: Associative DNN Inference Accelerator. - Leonid Yavits; Roman Kaplan; Ran Ginosar (CoRR, 2019)

RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping. - Roman Kaplan; Leonid Yavits; Ran Ginosar (IEEE Micro, 2019)

Adaptive programming in multi-level cell ReRAM. - Misbah Ramadan; Nicolás Wainstein; Ran Ginosar; Shahar Kvatinsky (Microelectron. J., 2019)

WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. - Leonid Yavits; Lois Orosa 001; Suyash Mahar; João Dinis Ferreira; Mattan Erez; Ran Ginosar; Onur Mutlu (ICCD, 2020)

BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data. - Roman Kaplan; Leonid Yavits; Ran Ginosar (SYSTOR, 2020)

A survey of algorithmic methods in IC reverse engineering. - Leonid Azriel; Julian Speith; Nils Albartus; Ran Ginosar; Avi Mendelson; Christof Paar (J. Cryptogr. Eng., 2021)

GIRAF: General Purpose In-Storage Resistive Associative Framework. - Leonid Yavits; Roman Kaplan; Ran Ginosar (IEEE Trans. Parallel Distributed Syst., 2022)

Theoretical complexity analysis of many-cores on a single chip. - Ran Ginosar (CoRR, 2025)