An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. - Xin Jiang 003; Ran Zhang 005; Takahiro Watanabe (ASICON, 2011)

A sorting-based IO connection assignment for flip-chip designs. - Ran Zhang 005; Xue Wei; Takahiro Watanabe (ASICON, 2013)

An Efficient Algorithm for 3D NoC Architecture Optimization. - Xin Jiang 003; Ran Zhang 005; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A randomized algorithm for the fixed-length routing problem. - Tieyuan Pan; Ran Zhang 005; Yasuhiro Takashima; Takahiro Watanabe (APCCAS, 2014)

A length matching routing method for disordered pins in PCB design. - Ran Zhang 005; Tieyuan Pan; Li Zhu; Takahiro Watanabe (ASP-DAC, 2015)

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. - Ran Zhang 005; Tieyuan Pan; Li Zhu; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2015)