Optical lithography simulation using wavelet transform. - Rance Rodrigues; Aswin Sreedhar; Sandip Kundu (ICCD, 2009)

A mask double patterning technique using litho simulation by wavelet transform. - Rance Rodrigues; Sandip Kundu (ACM Great Lakes Symposium on VLSI, 2010)

A study on performance benefits of core morphing in an asymmetric multicore processor. - Anup Das 001; Rance Rodrigues; Israel Koren; Sandip Kundu (ICCD, 2010)

Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. - Rance Rodrigues; Sandip Kundu; Omer Khan (ITC, 2010)

Optical Lithography Simulation with Focus Variation using Wavelet Transform. - Rance Rodrigues; Sandip Kundu (VLSI Design, 2010)

Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. - Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu; Omer Khan (PACT, 2011)

An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors. - Rance Rodrigues; Israel Koren; Sandip Kundu (PACT, 2011)

An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. - Rance Rodrigues; Sandip Kundu (Asian Test Symposium, 2011)

An Architecture to Enable Life Cycle Testing in CMPs. - Rance Rodrigues; Israel Koren; Sandip Kundu (DFT, 2011)

On graceful degradation of microprocessors in presence of faults via resource banking. - Rance Rodrigues; Sandip Kundu (IOLTS, 2011)

On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. - Rance Rodrigues; Sandip Kundu (IOLTS, 2011)

Model based double patterning lithography (DPL) and simulated annealing (SA). - Rance Rodrigues; Sandip Kundu (ISQED, 2011)

A mechanism to verify cache coherence transactions in multicore systems. - Rance Rodrigues; Israel Koren; Sandip Kundu (DFT, 2012)

Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt. - Arunachalam Annamalai; Rance Rodrigues; Israel Koren; Sandip Kundu (IPDPS Workshops, 2012)

Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency. - Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu (SBAC-PAD, 2012)

Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing. - Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu (ACM Trans. Design Autom. Electr. Syst., 2012)

An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs. - Arunachalam Annamalai; Rance Rodrigues; Israel Koren; Sandip Kundu (PACT, 2013)

A low power architecture for online detection of execution errors in SMT processors. - Rance Rodrigues; Sandip Kundu (DFTS, 2013)

On dynamic polymorphing of a superscalar core for improving energy efficiency. - Sudarshan Srinivasan; Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu (ICCD, 2013)

A study on polymorphing superscalar processor dynamically to improve power efficiency. - Sudarshan Srinivasan; Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu (ISVLSI, 2013)

A Study on the Use of Performance Counters to Estimate Power in Microprocessors. - Rance Rodrigues; Arunachalam Annamalai; Israel Koren; Sandip Kundu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency. - Sudarshan Srinivasan; Nithesh kurella; Israel Koren; Rance Rodrigues; Sandip Kundu (PACT, 2014)

Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores. - Arunachalam Annamalai; Rance Rodrigues; Israel Koren; Sandip Kundu (ISVLSI, 2014)

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core. - Rance Rodrigues; Israel Koren; Sandip Kundu (VLSID, 2014)

A low-power instruction replay mechanism for design of resilient microprocessors. - Rance Rodrigues; Arunachalam Annamalai; Sandip Kundu (ACM Trans. Embed. Comput. Syst., 2014)

A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors. - Abhisek Pan; Rance Rodrigues; Sandip Kundu (ACM Trans. Embed. Comput. Syst., 2015)

Does the Sharing of Execution Units Improve Performance/Power of Multicores? - Rance Rodrigues; Israel Koren; Sandip Kundu (ACM Trans. Embed. Comput. Syst., 2015)